[sdiy] Long LFSRs (Was Psych Tone)

[David Manley]

A maximal length LFSR by definition has 2^n - 1 states.

This means these LFSRs will - by definition - eventually create every 
pattern on N-bits, except for the '-1' state which is either all-0s or 
all-1's depending on whether XOR or XNOR feedback is used.

So for any maximal length LFSR it doesn't really matter where the taps 
are, eventually the states with many Consecutive Identical Digits 
('CID') will be emitted.  Different tap selections will just change the 
order in which the states are generated.

To put it in simpler terms: even a maximal length LFSR will generate a 
'1' followed by N-1 zeroes if you let it run long enough.  So a 127-bit 
LFSR will generate at some point these states (again not in this order, 
but at some point):

10000000000...0
11000000000...0
11100000000...0
...
11111111111...0
...
0...00000000111
0...00000000011
0...00000000001

They'll also generate:

10101010
01010101
11001100
00110011
etc...

LFSRs are commonly used for scramblers in bit-serial transmission 
protocols.  The CID problem is one factor that determines how good the 
PLLs used for clock and data recovery need to be.  For PLLs to operate 
they need edges to determine the phase of the received signal, and if 
you have too many consecutive identical digits, you have no edges, and 
the PLL can drift off phase/frequency if designed incorrectly.  Since 
the data being transmitted gets EXORed with the LFSR output you can also 
have CID if the data transmitted just happens to match the LFSR output.  
Typicaly this is avoided by using a data coding such as 8B10B or 64B66B 
where transitions are guaranteed to occur.

-Dave (seems like I've been dealing with bit-serial transmission 
protocols my whole career...)



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