[sdiy] Homemade Memorymoog - update
brianw at audiobanshee.com
Mon Feb 18 02:15:48 CET 2019
On Feb 17, 2019, at 3:55 PM, Luís Marka <luis.marka at terra.com.br> wrote:
> Short update: got the digital board pretty much done, here: https://imgur.com/a/luI6OHl
Looking nice. Very vintage!
> Not as compact as I thought it would be, but was a good training in using Kicad. Now ordering the parts, and making the final revision before sending the board for fabrication.
> Already started work on a more compact version of this board: SMD for some of the components, getting rid of the sequencer connector and replacing 3x 2532 EPROMS (already changed for the 2732 in my board, had a number of 2732 around and I already did manage to burn the firmware on those, so why not?) with one single 27C128. In the same line, would it be possible to replace the 4x 2k 6116 SRAMs with 1x 8k AS6C6264, for example? For reference, the Memorymoog memory control section is here: https://imgur.com/a/fnsf1qs
> Any help in implementing the logic for this reduced number of memory chips is much appreciated! In the mean time, will attack the PSU and DMUX boards.
The AS6C6264 looks like a good replacement for four 6116 chips. The first specific chip I found has a 55 ns access time, so you just have to confirm that the Memorymoog processor bus design doesn’t need faster SRAM access than your replacement.
I haven’t looked at the Memorymoog schematic (lately), but I assume that an address decoder of some kind is used to drive the OE (Output Enable) pin, one at a time, for the four 6116 chips. At the same time, I assume that the WE (Write Enable) pin is only driven for one chip at a time. If you put all SRAM in a single chip, then you’ll just need to modify the decoder logic as appropriate for OE and WE. All of the other pins should be the same, with the obvious addition of A11 and A12.
I’ve worked on a lot of vintage circuits with 6116 chips, but I’ve never designed something new around them. The first data sheet I saw mentioned that CS (Chip Select) puts the chip in power-down mode when deasserted. That’s a slightly alarming thing to read, because I’m not sure whether the SRAM would lose its contents in power-down mode. Another section of the data sheet calls this “standby” mode, so maybe that’s no problem.
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