[sdiy] LTSpice problem: simulating Irwin/Gallo linearised 2164 VCA

rburnett at richieburnett.co.uk rburnett at richieburnett.co.uk
Thu Aug 22 15:26:33 CEST 2019


Hi Tom,

That sort of error means that the simulator has gone down to like 
sub-picosecond time steps in order to try to solve the matrices that 
describe the nodal voltages and currents in the circuit and is still 
failing to come up with an acceptable solution.  This often happens with 
feedback loops where the simulator either struggles to determine the 
initial conditions of the circuit at time t=0 or it struggles to 
re-calculate all of the nodal voltages and currents again after a rapid 
switching transient.

Things you can try:

1. Try adding some small resistors in places around the feedback loop.  
Sometimes adding a series resistor with R=0.001 ohms will magically make 
the simulation run.
2. Try putting capacitors across the feedback resistors of op-amps to 
limit the bandwidth.  Otherwise the simulator might assume a very large 
bandwidth and therefore have to work with very small time steps in order 
to balance its equations.
3. Try using a lower slew rate for edges on signals that you generate 
which switch from one state to another.  If things change state more 
slowly it is easier for the simulator to keep up!  (i.e. Don't specify 
pico-second rise and fall times for a pulse generator unless you are 
actually simulating a properly modelled microwave circuit.)
4. Try to include as many parasitic R's and C's as the circuit really 
has.  These are what can ultimately determine the rate-of-change of 
signals in the otherwise ideal and boundless world of simulation.

A similarly cryptic error in Spice used to be the dreaded convergence 
error, where the matrices that the simulator comes up with to describe 
your circuit just fail to converge mathematically on a sensible answer!

-Richie,



On 2019-08-22 12:59, Tom Wiltshire wrote:
> Hi All,
> 
> I’m having trouble simulating the Irwin/Gallo linearised 2164 VCA. The
> error I get is: “Analysis: Time step too small; initial timepoint:
> trouble with node n005”
> 
> I don’t really understand what this is trying to tell me since the
> .tran transient analysis command I’m using is unchanged since a
> previous typical 2164 VCA where it worked fine.
> 
> I can simulate other circuits using the 2164 ok, so I’m wondering if
> it’s something particular to that circuit, and specifically whether
> the feedback loop needs dealing with some how differently?
> 
> Have other people managed to sim this circuit and if so, what did you 
> do?
> 
> Any pointers appreciated.
> 
> Thanks,
> Tom
> 
> 
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