[sdiy] BBD clock bleed

rsdio at audiobanshee.com rsdio at audiobanshee.com
Wed Oct 24 17:41:06 CEST 2018


On Oct 24, 2018, at 6:39 AM, Tom Wiltshire <tom at electricdruid.net> wrote:
> On 24 Oct 2018, at 12:33, Uwe Schueler <uwe.schueler at uni-tuebingen.de> wrote:
>> all suggested filter and companding stuff adds a lot of complexity and $s. Maybe for these $s you could add a 2nd BBD in parallel, fed by the inverted input signal and diff.amp the outputs. This should improve SNR by 6db and cancel a lot of clock feed through - in theory;-)
> 
> Now, this one Reticon did do. The SAD1024A is organised as a dual 512 stage device, and one of the suggestions in the datasheet is that it can be used as you describe.
> 
> http://www.pmerecords.com/Docs/Archer_SAD-1024_Tech_Data.pdf

In theory, the S/N would only improve by 3 dB, not 6 dB. Don’t forget that the 2nd BBD adds more noise! Since the signal is the same for both, the signal level is increased by 6 dB. Meanwhile, the noise is different for each, so the noise level increases by 3 dB. The resulting improvement to S/N is thus 3 dB.

However, the signal-to-clock ratio should improve by 6 dB. That’s because the clock will be the same for both chips. You just get 3 dB more non-clock noise.

Brian Willoughby




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