[sdiy] CMOS mystery

[David G Dixon]

Hey Team,

I built a couple of "Perfect fifth generators" for someone.  They are pretty
simple: you feed a 10Vpp triangle wave and an in-phase square wave in, and
you get a square wave out which is a perfect fifth higher in pitch.

Here's how it works (note, this is not my idea): The triangle wave is sent
to a comparator with a threshold voltage of about 1.67V, and this generates
a pulse wave of 1/3 duty cycle.  The square wave is sent to a ripple
counter, and this generates a suboctave square wave.  The 1/3 pulse wave and
the suboctave square wave are fed to either an XOR or an XNOR gate, and this
gives the perfect fifth.  Easy peasy.

I used a TL072 as the comparator, with a 10k output resistor dropping across
a 5.1V grounded zener to generate a 0-5V 1/3 duty cycle pulse.  The ripple
counter is of the 4024 variety.  For the XOR, I wired up a quad NAND gate
(4011) in the time-honored way.  For XNOR, a quad NOR gate (4001) may be
used instead.  I have used both and they both work well.  Ultimately I went
with the quad NOR XNOR gate because I had more than one 4001 chip.  Both the
4024 and the 4001/4011 are powered from a 78L05.  Finally, the output of the
XOR/XNOR is fed to the other side of the TL072, which is wired as a
non-inverting amp with a gain of 2, and with the output level-shifted -5V
from the 78L05 to give a perfect fifth square output which is 10Vpp and
centred around 0V.

So, here's my problem: If I use either an MC14024 or a CD4024BCN for the
counter, the circuit works perfectly.  If I use a CD4024BE, the circuit
doesn't work.  The outputs of all three counters look the same on my scope,
but the 4001 or 4011 outputs are all wrong for the one counter, and
perfectly correct for the other two.

Do any of you "gurus" have any insight as to why this might be?  I thought
that perhaps the 4001/4011 didn't like the zener-derived square wave,
because it would be perhaps slightly higher than 5V.  However, the
datasheets suggest that input voltages between -0.5V and VDD + 0.5V (which
would be 5.5V) are OK.  Could it be that the zener is only limiting the
"zero" voltage to about a diode drop below ground, and this is slightly
below -0.5V?  If so, then why would the choice of counter chip make any
difference?  The output of the counter is determined by the 5V supply (the
78L05), which is common to both CMOS chips.  Could the 4001/4011 be confused
by the two slightly different levels of the 1/3 duty cycle square wave and
the suboctave square wave?  If so, why would the counter chips be giving
different output voltages if they are all supplied by the same 5V supply?

I'm stumped.