[sdiy] Tri-core oscillator sync

David G Dixon dixon at mail.ubc.ca
Wed Dec 19 02:01:42 CET 2018


> Interesting.
> 
> I'm using a window comparator and a D flip flop to do the 
> switching. The comparators drive the set/reset inputs and the 
> hard sync drives the clock input. As I understand it this is 
> reversing sync. My soft sync drives the reference input on 
> the upper comparator on the window comparator, thus shifting 
> the upper trigger point.

Um.  Sounds complicated.  Mine is a fairly standard tri-square oscillator.
The integrator triangle output is summed with the square output (which gives
the famous "zigzag" waveform for free) and this drives the + input of the
comparator.  The - input is typically grounded (through a 1k resistor), and
the "reversing" sync input drives it through a 3.3nF capacitor.  The output
of the comparator is limited to +/-5V by one of those zener bridges we were
talking about last week, thus creating the square output.  This square wave
drives the integrator through a 2164 VCA acting as a 1V/oct expo converter,
thus closing the loop.  A linearized 2164 VCA in the loop provides linear
FM.  This is the basic Dixie VCO.

> My design has the cap voltage bouncing between two positive 
> points. If I add A reset FET the cap voltage will go to zero 
> which is below the lower set point. Do your designs have the 
> cap voltage going to zero as a matter of course?

Yes.  The triangle integrator's - input is grounded.




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