[sdiy] Help, I'm Desperate! (Charge Injection with DG408)

Steve Lenham steve at bendentech.co.uk
Tue Dec 4 11:12:04 CET 2018


On 04/12/2018 09:38, Guy McCusker wrote:
>> - Here is my main suggestion as to what it might be. It sounds like (we
>> only have your description of the circuit to go on) you are generating
>> the three-bit control word for the analogue switch from the outputs of
>> several analogue comparators. How sure are you that the transition from
>> one digital value to the next is clean, i.e. that all three bits change
>> state at exactly the same time? If the three-bit word passes through any
>> intermediate "runt" states on its way, the switch will briefly select a
>> completely different input and potentially inject spikes of something
>> else into the output. This is an issue in digital systems (search "race
>> hazards") and is likely to be even worse if comparatively slow and
>> imprecise analogue comparators are involved.
> 
> Ah, this is interesting. I am toying with something that involves
> switching with a DG408 too, and had started wondering about using a
> CMOS priority encoder (CD4532) to generate the three bit words from an
> analog select signal. Might something like that help to get clean
> switching signals here too?

It might, but it depends on how you generate the inputs to the priority 
encoder. The 4532 generates an output word corresponding to the highest 
of its eight inputs that is active. If more than one input is active, 
the highest priority input takes precedence (hence the name).

If you had a problem caused by your circuitry activating more than one 
control line simultaneously then the priority encoder might help. If, 
however, the input to the priority encoder travels through intermediate 
states on its way from one value to another then it will NOT help.

For example, if you want to switch from source 1 to source 7 but the 
input to the priority encoder briefly travels through 4 then the output 
of the encoder will faithfully follow that and you will be no better off.

The ideal - though not always possible - way to eliminate these 
intermediate states is to make the system synchronous. You feed the 
asynchronous address lines to the inputs of a D-type latch, then clock 
the latch at a point where you know that all the bits that were going to 
change have had time to do so. The output of the latch then drives your 
analogue switch (or whatever).

Of course, you can only do that if you know the point at which you 
expect the value to change, and it sounds from David's descriptions like 
that is not the case in his design.

If it looks like this might be the problem, we may need to see more of 
the circuit in order to suggest a solution in this case.

Cheers,

Steve L.
Benden Sound Technology





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