[sdiy] FPGA Madness? (Was: NCO Jitter)

Andrew Simper andy at cytomic.com
Tue Aug 7 03:20:56 CEST 2018


And don't forget DPW as an easy to implement method to reduce aliasing. You
can use an interpolated inverse table and the error only appears as slight
differences in amplitude, it doesn't reduce the efficacy of the
anti-aliasing (which is the case with BLEP if you don't have a good
division). As long as you can easily generate the intergrated waveshape
equation and compute that efficiently you can do DPW efficiently and it
will tilt the spectrum by -6 dB/Oct, which will reduce the oversampling
overhead considerably.

On Mon, 6 Aug 2018 at 08:49, <rsdio at audiobanshee.com> wrote:

> If you’re willing to consider building everything on an FPGA, then I
> suggest that you should definitely consider a DSP. You’ll get more bang for
> your buck with a DSP - unless you literally pay for an FPGA that has full
> DSP slices in it - and it will be easier to work in an instruction set that
> has been optimized for decades for exactly the kind of thing you’re doing.
>
> Top contenders would be the TMS320, especially the C5000 or C6000 series,
> and the SHARC.
>
> I addition to the math support and large accumulators, you’ll also get
> timer peripherals and serial ports that support digital audio connections
> to multi-channel DACs.
>
> I’ve done some complex designs, and using a DSP is basically as flexible
> as an FPGA without the overhead of creating or finding and adapting the
> various IP blocks. You’ll also have the benefit that there won’t be as much
> wasted power.
>
> Brian
>
>
> On Aug 3, 2018, at 8:50 PM, Tim Ressel <timr at circuitabbey.com> wrote:
> > I have a design for a complex VCO that will include 9 NCOs. While the
> polyBlep stuff looks interesting, I am wondering if I can pull it off with
> an FPGA. So the 9 NCOs would run at a high rate, say 2MHz. Then they get
> mixed, filtered, and downsampled to about 50KHz. The filter is the part I
> am not sure of, but its been done before so it is just a matter of working
> it out.
> >
> > I figure by the time I get a processor powerful enough to do this, and
> FPGA is cheaper maybe?
> >
> > Am I more out of my mind than usual?
> >
> > --
> > --Tim Ressel
>
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