[sdiy] New SPI SRAM

rburnett at richieburnett.co.uk rburnett at richieburnett.co.uk
Mon Aug 20 16:14:29 CEST 2018

My SPI SRAM samples arrived last week, but I haven't had time to test 
them out yet.

I just noticed in the datasheet about the device being a dual-die stack 
in one SOIC package.  There is a note about the implications of this.  
The device only has a single Chip-Select line, which is nice, but you 
can't do sequential reads or writes of data that span the half-way mark 
in the address space.  Sequential accesses beyond the end of the first 
half of address space wrap to the start of the first half (die "0"), and 
sequential accesses beyond the end of the second half of address space 
wrap to the start of the second half of address space (die "1").  Not a 
major problem if doing single-byte reads and writes to/from the device, 
but something to bare in mind if transferring larger blocks of data at 
once (which is much more efficient.)  Blocks that straddle the half-way 
mark would need to be handled with two separate commands, (or simply 
avoided altogether.)


> ISSI website is showing an interesting new half-Megabyte 8-pin serial 
> (SPI)
> Static RAM chip that might be of interest for audio processing:
> http://www.issi.com/WW/pdf/IS62-65WVS5128GALL-BLL.pdf
> I've had Microchip's 23LC1024 (128 Kilobyte SPI SRAM) working with 
> dsPIC
> using SPI via DMA,  so have requested a few samples of the ISSI part to 
> try
> it out.
> -Richie,

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