[sdiy] FPGA Madness? (Was: NCO Jitter)

Richie Burnett rburnett at richieburnett.co.uk
Sat Aug 4 12:18:16 CEST 2018


It sounds reasonable to me, but I'd try to get the sampling rate higher than a couple of MHz if you don't plan on doing anything else to reduce aliasing and plan to cover the full  midi pitch range. OTOH, If you're just making a bass synth then that will probably be more than adequate.

Also you might want to look at CIC filters for decimation as I am told that they are good for large decimation ratios and are relatively easy to implement in hardware on an FPGA.

-Richie,

Sent from my Xperia SP on O2

---- Tim Ressel wrote ----

>Hey all,
>
>I have a design for a complex VCO that will include 9 NCOs. While the 
>polyBlep stuff looks interesting, I am wondering if I can pull it off 
>with an FPGA. So the 9 NCOs would run at a high rate, say 2MHz. Then 
>they get mixed, filtered, and downsampled to about 50KHz. The filter is 
>the part I am not sure of, but its been done before so it is just a 
>matter of working it out.
>
>I figure by the time I get a processor powerful enough to do this, and 
>FPGA is cheaper maybe?
>
>Am I more out of my mind than usual?
>
>-- 
>--Tim Ressel
>Circuit Abbey
>timr at circuitabbey.com
>
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