[sdiy] FPGA Madness? (Was: NCO Jitter)

Gordonjcp gordonjcp at gjcp.net
Sat Aug 4 10:26:25 CEST 2018


On Fri, Aug 03, 2018 at 08:50:33PM -0700, Tim Ressel wrote:
> Hey all,
> 
> I have a design for a complex VCO that will include 9 NCOs. While
> the polyBlep stuff looks interesting, I am wondering if I can pull
> it off with an FPGA. So the 9 NCOs would run at a high rate, say

In my crappy Arduino implementation I used an 8-bit lookup table for the
polynomial and an 8-bit reciprocal table for the division.  Since there
are a lot of multiplies it's probably worth sticking with the lookup
table idea for the polynomial and maybe interpolating if you need better
resolution.  Dividing is a lot harder than multiplying, which is why I used
reciprocals.

Even if you used fairly "low resolution" correction factors, at 2MHz
your aliases are going to be way off in the weeds. Hell, even with naive
waveform generation.

-- 
Gordonjcp MM0YEQ




More information about the Synth-diy mailing list