[sdiy] FPGA Madness? (Was: NCO Jitter)

Tim Ressel timr at circuitabbey.com
Sat Aug 4 05:50:33 CEST 2018

Hey all,

I have a design for a complex VCO that will include 9 NCOs. While the 
polyBlep stuff looks interesting, I am wondering if I can pull it off 
with an FPGA. So the 9 NCOs would run at a high rate, say 2MHz. Then 
they get mixed, filtered, and downsampled to about 50KHz. The filter is 
the part I am not sure of, but its been done before so it is just a 
matter of working it out.

I figure by the time I get a processor powerful enough to do this, and 
FPGA is cheaper maybe?

Am I more out of my mind than usual?

--Tim Ressel
Circuit Abbey
timr at circuitabbey.com

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