[sdiy] dsPIC UART for multi-processor comms

Richie Burnett rburnett at richieburnett.co.uk
Sun Apr 22 17:44:36 CEST 2018


Maybe a signal integrity issue, (reflection due to poor termination) if the interconnections are quite long at the prototyping stage. But 100k baud is a bit slow to run in to these problems. Have you looked at the waveform arriving at the UART rx inputs when it works and then again when it isn't working. This should reveal what's going wrong.

You haven't tied multiple UART TX lines together somehow have you? 

Also, have you considered SPI instead? This is probably better for supporting a multi-drop network like this, if the slaves need to be able to send data back to the master too.

-Richie,

Sent from my Xperia SP on O2

---- Tom Wiltshire wrote ----

>Hi all,
>
>I’m currently experimenting with communications between multiple dsPICs. I have one master processor sending messages, and four slave processors receiving them. I have a fifth slave processor on the comms line which acts as a “comms monitor” dsPIC+LCD and just displays all traffic so I can see what’s going on.
>
>The UART is sending at 100KHz, and I’m using the 9-bit mode, which allows me to ignore data bytes which aren’t intended for a given processor - e.g. each processor only has to keep an eye out for address bytes and check those, rather than having to read every single byte that is sent.
>
>However - I’ve got a problem. Comms to each of the slaves works fine individually, but as soon as I stick a second or further chip in its socket, the comms stops working (Comms monitor registers no messages either) and the slaves do nothing. Currently, it only works with the master, one slave, and the monitor connected.
>
>What’s the maximum “fan out” for a UART like this? Do I need to buffer its output to get more drive or something? Why would connecting more inputs to the signal kill the comms?
>
>Any help or advice appreciated. I’m sure I’m not the first person to have come up against this type of problem…
>
>Thanks,
>Tom
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