[sdiy] Quality reverb on STM32's?

rsdio at audiobanshee.com rsdio at audiobanshee.com
Sun Apr 15 03:58:19 CEST 2018


Thanks again. Those two instructions - the LOG and EXP - do indeed represent a very optimized instruction set. I can’t say for sure that no other DSP has single-cycle log() or exp(), since it’s certainly possible to dedicate a lot of silicon to those useful calculations, but I’m not aware of one that does.

Many of the other instructions that they go on about in the FV-1 docs are quite common in typical DSP implementations, as Eric pointed out earlier. For example, automatic incrementing of the delay buffer pointers with power-of-two buffer size wraparound (common circular buffers) are a feature that is standard on DSP chips. The MAC in a typical DSP performs the equivalent of an entire loop of instructions on a general purpose CPU, except that the DSP does everything in parallel in a single cycle.

Brian


On Apr 14, 2018, at 3:58 PM, Neil Johnson <neil.johnson71 at gmail.com> wrote:
> Brian,
> 
> The LOG and EXP instructions are also single-cycle:
> http://www.spinsemi.com/knowledge_base/arch.html
> 
> Once you detach your brain from the "this is how DSPs are" train of
> thought you can start to play some interesting games - by specialising
> the instruction set the designers can spend more silicon implementing
> application-specific instructions in hardware-expensive but
> time-efficient ways.  In essence the FV-1 is an ASDSP
> (Application-Specific DSP).
> 
> Neil
> 
> On 14 April 2018 at 22:48,  <rsdio at audiobanshee.com> wrote:
>> Very interesting; both responses. Thanks.
>> 
>> One piece of information that is missing is how many clock cycles each instruction takes. While many of the instructions map directly to DSP opcodes that take a single cycle, I’m most curious about the LOG and EXP functions. In my experience, those are difficult to calculate, and require iterative algorithms. The problem with an iterative algorithm is that it takes way more than one cycle. If the FV-1 is able to compute LOG and/or EXP in a single cycle, then that would be an incredible advantage over a DSP (to my knowledge). Otherwise, if it takes a significant number of cycles then I don’t see how having a special opcode is much different from a subroutine on a DSP.
>> 
>> The TMS320 has the ability to cache an entire subroutine on the chip, after initially fetching the opcodes, and then loop through those instructions without any further program memory accesses. That alone speeds up things so much that you can flood the data memory busses unless you regroup and reoptimize.
>> 
>> In there information on the cycle counts for the FV-1 instructions? They look very promising.
>> 
>> Even if they’re equivalent to subroutines, it’s still probably a significant boost for development time since you can say what you need to say for reverb with fewer “words.”
>> 
>> Brian
>> 
>> In any case, I think that STM32 implementations of reverb will be significantly less efficient in one or more metrics.
>> 
>> 
>> On Apr 14, 2018, at 1:43 PM, Richie Burnett <rburnett at richieburnett.co.uk> wrote:
>>> Exactly what Eric said.  The FV-1 instruction set is specifically optimised for the job of chorus / flange and modulated reverb processing. It is most definitely not suited to many things that you might normally take for granted on a typical DSP. Processing audio in blocks of samples, for example.
>>> 
>>> As for the dsPIC, I find it very similar to analog devices' original 16-bit fixed point ADSP2181 DSP. Someone once described PICs to me as "almost a decent microcontroller", (...except for things like the quirky paged program memory, banked RAM etc.) In a similar way i'd describe dsPIC as "almost a decent DSP." I've used them in many commercial projects and they hit a certain price/performance point, but they have limitations, and are no TMS320 or SHARC.
>>> 
>>> I've got an ADSP21469 4th gen SHARC board here on my desk and it is a flying machine in terms of processing power, I/O bandwidth and flexibility compared to dspic. But they are in different price and complexity brackets of course.
>>> 
>>> -Richie,
>>> 
>>> ---- Eric Brombaugh wrote ----
>>>> On 04/14/2018 12:23 PM, rsdio at audiobanshee.com wrote:
>>>>> 
>>>>> The FV-1 has a DSP at its core. It seems entirely unlikely that it has an instruction set that is any more optimized for reverb than other modern DSP options.
>>>> 
>>>> Take a close look at the FV-1 ISA:
>>>> 
>>>> http://www.spinsemi.com/Products/datasheets/spn1001-dev/SPINAsmUserManual.pdf
>>>> 
>>>> * There are single op instructions specifically constructed to compute
>>>> all-pass filters and LFOs.
>>>> 
>>>> * There are built-in exponential and sinusoid lookup instructions.
>>>> 
>>>> * The memory architecture has been designed with a built-in
>>>> auto-incrementing offset pointer that allows construction of delay line
>>>> circular buffers with implicit pointer updates.
>>>> 
>>>> * The buffer memory is a quirky kind of floating point that's specially
>>>> designed for handling audio.
>>>> 
>>>> Granted - you can do all these things with a few instructions in a
>>>> standard DSP from ADI, TI or MCHP, but they haven't been quite so
>>>> strongly focused on reverb applications.
>>>> 
>>>> Eric





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