[sdiy] DCO Question

[Ben Bradley]

I forget where I read this, either the archives for SDIY or the
MUSIC-DSP list, but one way to do non-aliased waveforms with DDS and
wavetable lookup is (for each waveform) to have a separate wavetable
for every octave. The lowest octave(s) will use the full-bandwidth
wavetable, and the wavetables used in the higher octaves will be
bandlimited - the highest octave will be a sine wave, the second
highest also has the second harmonic of the original, the third
highest has the second, third and fourth harmonics, and so on. This
uses a lot more wavetable memory, but memory is a lot cheaper than it
used to be.

On Thu, Nov 2, 2017 at 5:57 PM,  <paula at synth.net> wrote:
> Sorry to disagree, it is doable on lower end micros 002 (8bit) uses NCOs and
> does not use an FPGA.
> You just need to find the right approach.
>
>
>
> On 2017-11-02 18:23, Tom Wiltshire wrote:
>>
>> +1 Agree. Brute force oversampling is rarely a great solution. Only
>> the Novation Peak has ever made this work effectively, and that was on
>> an FPGA.
>>
>> The irony for me is that the NCO’s “native” waveform is the ramp
>> generated by the incrementing phase, and that is just about the worst
>> case scenario from an aliasing point of view.
>>
>> One nice trick that I’ve seen is to output a triangle wave (and
>> thereby massively reduce the aliasing since the harmonics rolloff so
>> much faster)and then the rest of the wave shaping as if it were a
>> standard analog triangle-core oscillator.
>>
>>
>>> On 2 Nov 2017, at 17:58, Richie Burnett <rburnett at richieburnett.co.uk>
>>> wrote:
>>>
>>> Yes, but this kind of brute force oversampling is quite inefficient in
>>> terms of benefit vs CPU cycles burned. You have to go to sample rates up in
>>> the MHz if you want to cover the full MIDI note range with a naive NCO based
>>> sawtooth and get decent alias suppression. Not a problem for dedicated
>>> hardware like an FPGA, but taxing for a low end micro.
>>>
>>> -Richie,
>>>
>>> Sent from my Xperia SP on O2
>>>
>>> ---- John Speth wrote ----
>>>
>>>> If we're talking about the classic NCO/DDS model, can't the unwanted
>>>> effect be reduced by using more bits and a faster clock?
>>>>
>>>> -----Original Message-----
>>>> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of
>>>> Tim Ressel
>>>> Sent: Thursday, November 02, 2017 8:27 AM
>>>> To: SYNTH DIY <synth-diy at synth-diy.org>
>>>> Subject: [sdiy] DCO Question
>>>>
>>>> Hi,
>>>>
>>>> I am making a digital oscillator (DCO) and was wondering if there is a
>>>> way to reduce the jitter one gets at higher frequencies. I understand it
>>>> comes from round off error (for lack of a better term): as the accumulator
>>>> reaches the top of the range the remaining amount is less than the value
>>>> being added, and that fraction changes every cycle. This causes jitter, or
>>>> is it aliasing? Anyway, is there a clever way to deal with it?
>>>>
>>>> Thanks!
>>>>
>>>> --
>>>> --Tim Ressel
>>>> Circuit Abbey
>>>> timr at circuitabbey.com
>>>>
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