[sdiy] DCO Question

[Richie Burnett]

> The irony for me is that the NCO’s “native” waveform is the ramp generated 
> by the incrementing phase, and that is just about the worst case scenario 
> from an aliasing point of view.

But, it's really handy as an address pointer for accessing wavetable ROM 
though ;-)

> One nice trick that I’ve seen is to output a triangle wave (and thereby 
> massively reduce the aliasing since the harmonics rolloff so much 
> faster)and then the rest of the wave shaping as if it were a standard 
> analog triangle-core oscillator.

Most DDS based signal generators (like HP/Agilent/Keysight's 33250A) use the 
NCO staircase to generate a discrete-time sinewave via a Look-Up Table. 
This is then smoothed into a continuous-time sinewave using an analogue 
low-pass reconstruction filter (or "anti-imaging" filter if you prefer which 
acts to remove the repeating high-frequency images from the sampling 
process.)  The continuous-time analogue sinewave is then passed through a 
comparator to produce a square-wave that is free of aliasing / jitter. 
Essentially because the input to the comparator is a smooth continuous-time 
sinewave, then the transitions of the square-wave output are not forced to 
coincide with the edges of the NCO clock, so it is free of jitter if the 
reconstruction filter is designed properly.  (Compare this with just taking 
the MSB of the NCO accumulator to generate a square wave, which is plagued 
with jitter/aliasing.)  In this way, the generator can generate alias-free 
sine, square and pulse waveforms to micro-Hz accuracy from DC up to 10's of 
MHz.

-Richie,


> On 2 Nov 2017, at 17:58, Richie Burnett <rburnett at richieburnett.co.uk> 
> wrote:
>
> Yes, but this kind of brute force oversampling is quite inefficient in 
> terms of benefit vs CPU cycles burned. You have to go to sample rates up 
> in the MHz if you want to cover the full MIDI note range with a naive NCO 
> based sawtooth and get decent alias suppression. Not a problem for 
> dedicated hardware like an FPGA, but taxing for a low end micro.
>
> -Richie,
>
> Sent from my Xperia SP on O2
>
> ---- John Speth wrote ----
>
>> If we're talking about the classic NCO/DDS model, can't the unwanted 
>> effect be reduced by using more bits and a faster clock?
>>
>> -----Original Message-----
>> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Tim 
>> Ressel
>> Sent: Thursday, November 02, 2017 8:27 AM
>> To: SYNTH DIY <synth-diy at synth-diy.org>
>> Subject: [sdiy] DCO Question
>>
>> Hi,
>>
>> I am making a digital oscillator (DCO) and was wondering if there is a 
>> way to reduce the jitter one gets at higher frequencies. I understand it 
>> comes from round off error (for lack of a better term): as the 
>> accumulator reaches the top of the range the remaining amount is less 
>> than the value being added, and that fraction changes every cycle. This 
>> causes jitter, or is it aliasing? Anyway, is there a clever way to deal 
>> with it?
>>
>> Thanks!
>>
>> --
>> --Tim Ressel
>> Circuit Abbey
>> timr at circuitabbey.com
>>
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