[sdiy] DCO Question

[Richie Burnett]

Yes, but this kind of brute force oversampling is quite inefficient in terms of benefit vs CPU cycles burned. You have to go to sample rates up in the MHz if you want to cover the full MIDI note range with a naive NCO based sawtooth and get decent alias suppression. Not a problem for dedicated hardware like an FPGA, but taxing for a low end micro.

-Richie,

Sent from my Xperia SP on O2

---- John Speth wrote ----

>If we're talking about the classic NCO/DDS model, can't the unwanted effect be reduced by using more bits and a faster clock?
>
>-----Original Message-----
>From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Tim Ressel
>Sent: Thursday, November 02, 2017 8:27 AM
>To: SYNTH DIY <synth-diy at synth-diy.org>
>Subject: [sdiy] DCO Question
>
>Hi,
>
>I am making a digital oscillator (DCO) and was wondering if there is a way to reduce the jitter one gets at higher frequencies. I understand it comes from round off error (for lack of a better term): as the accumulator reaches the top of the range the remaining amount is less than the value being added, and that fraction changes every cycle. This causes jitter, or is it aliasing? Anyway, is there a clever way to deal with it?
>
>Thanks!
>
>--
>--Tim Ressel
>Circuit Abbey
>timr at circuitabbey.com
>
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