[sdiy] DCO Question

[Tim Ressel]

Ah, so if I am understanding polyBlep, one sacrifices waveform linearity 
i.e. spectral purity for jitter reduction. The last few samples get 
morphed so that the accumulator maxes out every cycle. In this case the 
saw wave will nose over a bit at the top. Another way of saying it is 
the fraction left at the top is amortized over a few samples. Since I am 
not trying to hit exact frequencies this should work nice and easy.

I don't want to calculate polynomials in floating point on the fly so I 
think I'll pre-calculate a table. Flash memory is cheaper than cycles.

Thanks!

-t-i-m-b-o-


On 11/2/2017 8:39 AM, Eric Brombaugh wrote:
> Jitter / Aliasing - it's both!
>
> Eliminating that "feature" of digital oscillators is the primary 
> motivation behind the proliferation of antialiased oscillator 
> algorithms and the proliferation thereof. Check out all the papers on 
> BLEP, MinBLEP, PolyBLEP, DPW, etc.
>
> Eric
>
> On 11/02/2017 08:26 AM, Tim Ressel wrote:
>> Hi,
>>
>> I am making a digital oscillator (DCO) and was wondering if there is 
>> a way to reduce the jitter one gets at higher frequencies. I 
>> understand it comes from round off error (for lack of a better term): 
>> as the accumulator reaches the top of the range the remaining amount 
>> is less than the value being added, and that fraction changes every 
>> cycle. This causes jitter, or is it aliasing? Anyway, is there a 
>> clever way to deal with it?
>>
>> Thanks!
>>
>
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-- 
--Tim Ressel
Circuit Abbey
timr at circuitabbey.com