[sdiy] DCO Question

[Tristan]

I suppose it could best be described as jitter, although directly outputting the accumulation counter as a 
sawtooth waveform would result in aliasing. If the counter is used as an index on a sine wavetable then 
the effect is to create sideband distortion in the output waveform based on the difference between the 
clock and synthesized waveform frequency. 

Two ways to get around it, or at least reduce the audible byproducts, are to use interpolation in your 
waveform synthesis to compensate for the timing errors with respect to the clock or to use dithering of 
the waveform synthesis timing with respect to the clock to convert the sidebands into something closer to 
random noise.

That said, there have been many synths which just output the synthesized waveform "jitter and all" such 
as the Ensoniq Mirage. It is crunchy but that can also be thought of as character ;)

/Tristan

On Fri, Nov 3rd, 2017 at 2:26 AM, Tim Ressel <timr at circuitabbey.com> wrote:

> Hi,
> 
> I am making a digital oscillator (DCO) and was wondering if there is a 
> way to reduce the jitter one gets at higher frequencies. I understand it 
> comes from round off error (for lack of a better term): as the 
> accumulator reaches the top of the range the remaining amount is less 
> than the value being added, and that fraction changes every cycle. This 
> causes jitter, or is it aliasing? Anyway, is there a clever way to deal 
> with it?
> 
> Thanks!
> 
> -- 
> --Tim Ressel
> Circuit Abbey
> timr at circuitabbey.com
> 
> _______________________________________________
> Synth-diy mailing list
> Synth-diy at synth-diy.org
> http://synth-diy.org/mailman/listinfo/synth-diy
> 
>