[sdiy] Modern codecs in variable-rate digital delay?

[John P Shea]

Does anyone know if the DM2000 uses a variable cutoff anti-aliasing filter??

Regards,
JPS

On Thu, 23 Mar 2017 at 6:32 am, Eric Brombaugh <ebrombaugh1 at cox.net> wrote:

> Tom,
>
> I don't see any reason why the codec would care - as far as I know it's
> all synchronous logic inside with no PLLs or anything that might lose lock.
>
> If you use a codec like that then you'll probably want to generate the
> MCLK (master clock) in the dsPIC anyway, so the only limitation is how
> well the main clock PLL in the dsPIC can tolerate variations of its
> reference frequency. If you slew too quickly it may lose lock and
> re-acquire which will cause all sorts of "fun" things to happen. If you
> control the slew rate on the VCO driving the dsPIC reference input then
> that may not be a problem.
>
> Eric
>
> On 03/22/2017 01:05 PM, Tom Wiltshire wrote:
> > Hi All,
> >
> > After my recent efforts building a fixed-sample-rate digital delay with
> only a dsPIC and SRAMs, I'm looking again at the problem.
> >
> > One of my original goals was to produce a functional clone of something
> like the Ibanez DM2000, which is a late 1980's 12-bit rack delay with
> companding. The significant thing about it is that it is a variable-rate
> sampling system. It has delay time modulation which is able to shift the
> sampling rate from a centre point of 64KHz up or down an octave (32-128KHz).
> > I didn't manage anything like this, as in the end I used a fixed rate.
> However, I'm reconsidering.
> >
> > Would it be possible to use a modern delta-sigma-type codec with a
> variable rate like this? For example:
> >
> >       http://www.cirrus.com/products/cs4270/
> >
> > Many of these chips have an upper limit of 192KHz or so, so the rates
> are no problem. It would be possible to feed them data from a dsPIC also on
> a variable clock - this would give the same effect as the original system,
> where modulating the master clock causes *everything* to change rate.
> >
> > Is there any reason why a modern codec would not be able to cope with
> this? Would there be upper or lower limits on modulation speed? The dsPIC
> can use an internal PLL to boost its clock frequency, and that PLL would
> have an effect on the modulation that was possible. Do codecs commonly do
> anything similar?
> > Another potential problem would be building a VC oscillator/clock that
> could reach the required speeds, since many chips seem to need master
> clocks of Fs x64 or more. That's getting up into the ten+ MHz range.
> >
> > It seems crazy that in this day and age it would be difficult to
> recreate technology from 25-30 years ago, but pretty much all modern
> systems seem to be aimed at a fixed rate, and variable rates are
> implemented by doing sample-rate interpolation rather than genuinely
> altering the rate.
> >
> > Thanks,
> > Tom
> >
> >
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