[sdiy] Analysis of the TB-303 CPU timing

[Magnus Danielson]

Hi Julian,

On 03/16/2017 12:43 PM, Julian Schmidt wrote:
>
> Am 15.03.2017 um 17:13 schrieb Bruno Afonso:
>> 3) you mention jitter several times but there is no statistical
>> description of the phenomena (mean, std dev, etc) or even a graphic
>> depiction such as an histogram. Without this it's hard for the reader
>> to see how relevant it may or not be.
> I calculated the standard deviation and mean value for the delay between
> the tempo clock and the gate signal and added a nice diagram to the PDF.
> I also added some diagrams showing the total on and off times for the
> gate signal at 2 different speeds.

I think the plot in Fig 2 shows the typical waiting jitter (I work on 
jitter in telecom, audio, broadcast and datacom stuff when I'm not 
looking into jitter and wander of clocks, so my pattern recognition says 
waiting jitter), which is also the type of mechanism we expect, so it 
matches.

The statistical measurement relevant would be the min delay, max delay 
and peak-to-peak delay variation. Statistical deviation isn't 
particularly useful here, but a histogram may give a better hint.

Since the ISR has a length matching the peak-to-peak range, it is fair 
to assume it is the waiting jitter for the ISR to occur. Thus, what you 
can do is to measure the time from Interrupt to start and Interrupt to 
stop. With that you can separate the waiting jitter due to trigger to 
interrupt time from that of delay and processing variations.

Another aspect is that the oscillator runs with 2.2 us period. One 
machine cycle is 4 clock periods, or about 8.8 us. Instructions is 1/2 
to 4 cycles. You can start making a bit of estimation to the processing.

Oh, and some jitter will be alignment to the 2.2 us clock.

You should be able to figure out quite a bit from the details of the 
timing and combining that with the knowledge of what it do and has to do.

Cheers,
Magnus