[sdiy] 4046 in VCOs (was Hi frequency VC clock)

Magnus Danielson magnus at rubidium.dyndns.org
Sat Jun 24 23:11:58 CEST 2017


Hi,

On 06/24/2017 12:30 AM, Tom Wiltshire wrote:
> Hi Tim,
>
> Sorry, I didn't realise that was something not widely known. Texas do one too:
>
> 	http://www.ti.com/product/LM331
>
> As it happens, this evening I've been looking at the high frequency VC clock (4MHz) design in the Elka Synthex which is based on that very chip.
>
> 	http://www.synfo.nl/servicemanuals/Elka/SYNTHEX_SCHEMATICS.pdf
>
> You want page 17, the 5840 schematic.

The Elka Synthex only uses the chip in a relatively small range, as it 
then does top octave divide down approach PER DCO. Modulations go into 
the high frequency clock, TTL dividers divide down for tone and octave, 
and then yet another for digital and analog wave-shaping, yes it 
actually do a little of both.

The last counter in the chain essentially acts exactly as the phase 
accumulator of the VCO charging cap, and much of the wave-shaping done 
digital is similar enough to what is done in analog. The ring-mod flips 
the sign, so it has that harsh square-wave ring-mod sound, which has it 
uses but not of my liking for everything. The PWM is done using an 
analog comparator, nothing really revolutionary.

Since the design is such a mix, it can be a bit daunting at first to get 
an overview, but it is kind of neat. Much of the digital stuff we would 
do in FPGA these days. Rather than divide down a DDS approach would be 
used to replace three divide down chains.

Would still be nice to have one.

Cheers,
Magnus



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