[sdiy] Synthex Oscillator

[rsdio at audiobanshee.com]

On Jul 12, 2017, at 1:04 AM, Tom Wiltshire <tom at electricdruid.net> wrote:
> I'd be interested to see the LTSpice sim too, if you don't mind sharing, Neil.
> 
> What did you learn about it? What's the advantage over a simple voltage-output DAC? What did you do with the transistor/cap reset? What signals did you use to reset the cap?
> Also what assumptions did you make about the pulse train driving the counter? It struck me that looking at the counter alone ignores the fact that the pulses going to it aren't nice and constant. Instead, the upper divider section provides the right *average* number of pulses to get the correct output frequency, but they're not evenly distributed. Instead, you get a variable-length "dead patch", followed by 128 clocks.

I didn't notice the significance of your final comments, Tom, the first time around (I was in the midst of my analysis when your email arrived), but it appears that we both reached similar conclusions about the erratic nature of the octave divider.

If this were a 1-bit PCM DAC, then perhaps it wouldn't matter that the pulses aren't evenly distributed. That hypothetical would require that each period contribute to a single sample, with the total number of pulses affecting the final Voltage. We have multiple examples of 1-bit PCM which each use different distributions of pulses to obtain the converted output. For example, the typical 8-bit sigma-delta DAC has 256 equal time slots where the input code determines the number of consecutive time slots that are High, with the remainder being Low. With some capacitance, this technique provides a very linear output Voltage, although the choice of clock rate has consequences. Another example 8-bit DAC has only 8 times slots, each with a time duration that is binary weighted with respect to the others. In this latter example, there can be 0 to 8 time slots that are High, but they do not have to be consecutive. Because of the binary weighting of the time durations, there can be 256 different output Voltages from an 8-bit digital input.

I mentioned all of the above just for fun, and also to point out that there are circuits where the only thing that matters is the relatively-longer-term average instead of perfectly regular timing.

In contrast, our Synthex circuit has been described as a digital oscillator with a counter instead of a lookup table. Well, if that were precisely true, then the non-continuous sample rate would really pose a problem with the wave shape. This would effectively hold the first sample in the waveform for a selectable number of clocks, and I don't see how that would produce either a ramp or triangle, since neither of those has a steady state. In addition, unless the schematic is in error, half of the down-counters have no CLEAR input, and thus would hold an arbitrary sample for a significant amount of time!


I'm going to throw out another wild idea out there:

Assuming that the DAC counter is CLEAR at the start of each cycle, then perhaps the goal of the digitally-controlled current sink is to start out with the natural RC decay while the counter is frozen, and only after that programmable number of cycles does the resistor array start manipulating the RC decay to charge the curve. I believe that the first part of an RC decay can be approximated as linear, so perhaps the circuit design goal is to hold off manipulating the curve until after it stops being basically linear. I'll have to do some more analysis to see if this holds. Clearly, the "DAC" behaves quite differently at different frequencies.


The SPICE simulation runs so slowly that I'm almost tempted to write a software application to model the digital components and then calculate the analog output based on the digital control signals.

Brian