[sdiy] Synthex Oscillator

[rsdio at audiobanshee.com]

This is getting complicated, so I must be overlooking something. I’ll go through what I’ve figured out by commenting inline below.

On Jul 8, 2017, at 1:16 AM, Tom Wiltshire <tom at electricdruid.net> wrote:
> As I understand it, the LS161 counters run as an 8-bit divider. The frequency divider value from the latches is used as the reset value, so the counter counts up from there, and the effective division is (256-divider).
The frequency divider is only 6 bits, not 8. The MSB, pin 6 of 2D, is tied to ground. In other words, the maximum value is 127, so (256-divider) is /129, not /1. The 4 MHz clock is brought down to between 15.625 kHz and just over 31 kHz. That represents almost an octave, so I guess it works.

> The LS112 flip flop can be enabled to change the lowest bit of the division value on alternate cycles, effectively giving a x0.5 division. This is used to increase accuracy without dividing the count down further.
> 
> On the right, in the blue box, is another counter, used to determine the octave. This is pretty straight-forward. It's  a binary counter followed by a 8-to-1 multiplexer to select the required octave.
I see a big problem here. The LS393 CLEAR is active high. Due to the pre-load value for the LS161 counters, Q3 (2D pin 11) starts out Low, but is inverted by 2G to be High. This effectively holds the LS393 counters at 0x00 via CLEAR until the LS161 counters reach a value of 0x80.

I can’t quite visualize the purpose of this variable pulse width counter enable. Can anyone tell me what I’m missing?

> The highest octave is fed directly from the clock. Ok, *almost* directly. And here's where things get interesting.
> 
> There's another little red box containing a single NOR gate. Now this NOR gate means that when pulses come in from the first divider, the clock pulse to the second (blue) counter) disappears. I understand this is known as a "pulse swallowing counter”.
I don’t think it works like that. While the NOR gate is swallowing clocks from CP1, the LS393 is held in CLEAR anyway, so I don’t see how it much matters.

> Note that the second counter is not *clocked* by the first one, but is rather *cleared* by it (LS393, pins 2 and 12). It's clocked only from the 4MHz master clock via that NOR gate. If I'm getting it right, instead of giving you 1/255th of the input frequency, it gives you 254/255ths of the input frequency (for example) because every 255th pulse gets swallowed.
Note that Q3 from the first counter is Low from the moment it’s pre-loaded until its count reaches 0x7F. Then, Q3 is High until it wraps around to 0x00 (0x100) when the TC output causes the !PL input to trigger the load again.

This tells me that there is a programmable period, between 1 and 128 clocks, when the second counter is held in CLEAR, followed by a non-programmable period which is always 128 clocks when the second counter is incremented at the ~4 MHz rate. Only the second part of this pattern can be octave divided by the LS393. I swear that I must be missing something, because I don’t see how this works. Perhaps there are more errors in this schematic than I have already pointed out.

> That determines the basic pitch, I think.

One thing seems certain. Bit D4 of the OCTA1 register must be an oscillator enable. If it is low, then no clocks make it through at all, and the oscillator is disabled (and I believe that the ramp capacitor would either charge or discharge completely, depending upon where the DAC counter stopped, except for the DAC counters that have connections to their CLEAR inputs and receive a signal there). Therefore, I assume that OCTA1.D4 must be High to enable the oscillator, and that’s how I’m analyzing the circuit.

Someone please tell me that you have a Synthex and can verify this misleading schematic!

Brian Willoughby