[sdiy] Synthex Oscillator

[rsdio at audiobanshee.com]

To anyone who is trying to decipher the Synthex schematic, I’d like to warn you all that there are a number of misleading errors in the full schematic that are notably present on the color-coded excerpt that started this thread as well as many in the other oscillator sections. Another interesting note is that the service manual starts by referring to the 16 Synthex oscillators as digital.

• The first thing I noticed is that MR2 exists twice. I assume that one of the voices would label this MR1 at 2G output pin 12. The true MR2 is at 6G pin 12.

• H2 also exists twice. 3I output pin 7, Q3, should be labeled H1. 7I output pin 7 is the true H2.

• The resistor ladder counter at 2I+1I has its CLEAR inputs grounded, and I now assume they should be connected to MR1 although I’m not absolutely certain of this.

• The resistor ladder counter at 3I+4I has its CLEAR inputs driven by MR2, which should be labeled MR1.

• The resistor ladder counter at 6I+5I does not even show its GND inputs! It appears that the CLEAR inputs are grounded. This could mean that it’s identical to 2I+1I appears to be, but there are enough errors overall to leave this as an open question.

• The resistor ladder counter at 7I+8I has its CLEAR inputs driven by MR2 (probably the only section with no errors).

These last four inconsistencies make it difficult to tell whether the down-counter is free-running in half the examples, or if they’re supposed to all have a CLEAR signal coming from somewhere.

It’s apparent that a rising edge on the MSB of 6I causes 5H output pin 4 to reset the ramp C127. If SYNC is enabled, then MR2 is also triggered unless 8H output pin 1 is low (after the counter underflows). The circuit is a little different for a rising edge on the MSB of 7I, which only causes 5H output pin 11 to reset the ramp C143 if SYNC is high.

I still have some analysis to do, but I wanted to share these schematic errors first.

Brian Willoughby

p.s. Although not strictly an error, did anyone notice that the pre-load values for the first clock divider are bit-reversed? From LOAD MSB to LSB, they’re STA1.D4 D5 D6 D7 and OCTA1.D2 D3 (the lowest bit is optional fractional bit). The address bits for the LS151 selector are also scrambled, from MSB to LSB as OCTA.D7 D5 D6. I imagine that these two anomalies require some confusing firmware code. I suppose these all might be due to layout issues that were common for single-sided and even some two-sided boards.