[sdiy] Novation peak NCOs

[James J. Clark]

I originally tried an on-chip sigma-delta followed by an analog lowpass. I 
found the result to be quite noisy, even with a 3rd order loop. There was 
also an issue of some distortion caused by differences in rise time and 
fall time of the fpga digital outputs. This can be handled by encoding the 
bitstream, but lowers the data rate. Also, I didn't do any dithering, so 
there was probably some fixed pattern noise.

I could only get 6-8 bits worth using an on-chip sigma-delta. The external 
sigma-delta DAC chips are much better. The Cirrus chips we use are 
multi-bit sigma-delta, meaning that they combine sigma-delta with multibit 
converters in the loop. In this way the sigma-delta doesn't need to 
provide all of the bits. Also, the sigma-delta filters are 
presumably optimized in a way that I don't have the experience to 
duplicate.

I wouldn't recommend doing an on-chip sigma-delta conversion, unless you 
are only shooting for 8 bits or so. For higher bit-widths I would rather 
leave the conversion to the pros.

Jim


On Sat, 22 Apr 2017, Olivier Gillet wrote:

>> They probably do as I do on the Cyclebox, which is run everything at 24MHz
>> then decimate (subsample) to 96KHz (or whatever the DAC SR is) to feed into
>> the oversampled DAC.
>
> I don't think there's a need for a DAC at all. They just run the
> sigma-delta loop(s) in the FPGA, taking the already oversampled signal
> as input, and directly produce a 1-bit stream at 24 MHz straight from
> a FPGA pin - that is externally low-pass filtered.
>
> It would be inefficient (and would introduce some unnecessary latency
> due to filter length) to downsample to 96kHz in the FPGA, then
> re-upsample to MHz in the DAC.
>