[sdiy] Novation peak NCOs

[Olivier Gillet]

> They probably do as I do on the Cyclebox, which is run everything at 24MHz
> then decimate (subsample) to 96KHz (or whatever the DAC SR is) to feed into
> the oversampled DAC.

I don't think there's a need for a DAC at all. They just run the
sigma-delta loop(s) in the FPGA, taking the already oversampled signal
as input, and directly produce a 1-bit stream at 24 MHz straight from
a FPGA pin - that is externally low-pass filtered.

It would be inefficient (and would introduce some unnecessary latency
due to filter length) to downsample to 96kHz in the FPGA, then
re-upsample to MHz in the DAC.