[sdiy] Novation peak NCOs

[Eric Brombaugh]

As Neil noted earlier, "hardened" I2C and SPI means that there are IP 
cores for these functions included on the part which are built with 
dedicated circuits and don't require you to code them up on the FPGA 
fabric. I haven't used these in any of my work as I already have a SPI 
interface that works for my purposes and the hardened blocks have 
features I don't need that makes controlling them more work than I 
wanted to do.

Although I haven't tried it, I suspect that the 1K part should drop 
right in to that board without changes.

Eric

On 04/21/2017 01:42 AM, Phillip Harbison wrote:
> Eric Brombaugh wrote:
>> https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE5LP1K-SG48ITR50/220-2064-1-ND/5358105
>>
>
> Interesting part. Do you know what they mean by "hardened" I2C and
> SPI interfaces?
>
>> http://ebrombaugh.studionebula.com/embedded/f303_ice5/index.html
>
> I've been looking for a hardware design project to get my feet wet
> again. Perhaps a version of this for the 1K part?
>