[sdiy] SHARC DSP programming
rburnett at richieburnett.co.uk
Wed Sep 28 13:19:52 CEST 2016
> I'm more of a TMS320 expert, where there is a bit-shift option on the MAC
> instruction as well as many other instructions that operate on the full
> 40-bit accumulator width. This option is rather limited, though, allowing
> only 1 bit shift, not any more. It's called FRCT mode.
The SHARC offsers the same thing. It shifts the multiply result left one
place when you tell it that you're working with Q1.31 fixed-point
fractionals to suppress the extra sign-bit that would otherwise be generated
in the result. I'm implementing that already.
> ...What might be the case is that fixed-point developers are expected to
> scale all of the processing stages so that the final output is in range
> for being quantized to the smaller, general-purpose registers. Not quite
> sure how to accomplish that with their instruction set, but perhaps it's a
> matter of scaling the coefficients before applying the MAC or other
Yes, I see what you are saying, that may indeed be their viewpoint.
However, with Q1.31 (1 sign bit, 31 fractional) fixed-point fractional
format you can only specify coefficients between -1 and +1, so for instance
when mixing multiple signal sources it's hard to get a gain of more than 1.
What I'm used to is being able to apply 2 left shifts to the mix sum in the
MAC accumulator (80-bits) to get a gain of 4 before saturating and rounding
this value back to 32-bits. The two left shifts to the total effectively
make the mix coefficients Q3.29 format (1 sign bit, 2 whole and 29
fractional) so I can get gains between -4 and +4. What I'm wanting to do
really isn't that unusual because the coefficient range for standard
bread-and-butter DF1 biquad implementations is -2 to +2, so I thought there
would be built in support for normalising to this range in fixed-point mode!
I'll have a look for some more of ADI's examples. Then I'll just have to
work around this limitation in fixed-point calculations, or switch them to
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