[sdiy] Dual Transistor Expo-Converter Question
rburnett at richieburnett.co.uk
Sun May 22 23:21:25 CEST 2016
> Is that really dominant-pole compensation?
Ermm, I *think* so if the added capacitance is large enough, but you might
be right. (You've got me questioning it now after reading that TI App
It definitely compensates for the pole in the feedback path due to the
capacitance of the transistors combined with the 4k7 resistor. Does it do
that by rolling off the gain at a sufficiently low frequency before the
phase shift from the second unwanted pole has chance to kick in? ...or does
it compensate for the phase-lag introduced by the unwanted capacitance and
the 4k7 resistor.
I'd have to generate the bode plots and do the maths to be 100% sure...
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