[sdiy] Non maximal-length LFSR

[Magnus Danielson]

Dave,

You have to realize I work with time and frequency too ;-)
However, We've been doing that for about 10 years, which is a minor 
eternity in this industry.

The 25 G serdeses is then  operated with some phase-shift to keep 
pumping 100 G. 40 G pipes has been around for some time, but is starting 
to become more common now.

A long time ago I posted a bunch of noise polynomials that where so long 
(yet simple) that is so long that even if operated, they would cover the 
expected lifetime of the sun and earth, so looping artefact's becomes a 
moot detail.

Cheers,
Magnus

On 03/05/2016 06:28 PM, Dave Manley wrote:
> "minor eternity" ;-)
>
> And 25G serdes are here now in CMOS for those who need and can afford it.
>
>
>
> On March 5, 2016 9:13:41 AM PST, Magnus Danielson <magnus at rubidium.dyndns.org> wrote:
>> Indeed. We now run STM-64 (10 Gb/s) in CMOS since minor eternity (using
>>
>> parallel scrambling).
>>
>> Cheers,
>> Magnus
>>
>> On 03/05/2016 06:05 PM, Dave Manley wrote:
>>> I brought it up in this context only because many comments were made
>> that you only get one new bit per shift - true for single bit shifts
>> but overlooks multi bit shifts. It is an aside to the original topic.
>>>
>>> And yes, what I described is more typically done in digital logic.
>> Running a parallel scrambler at the bit rate div 16, 32, or 128 is much
>> easier to implement in today's CMOS processes than a serial scrambler
>> when the serial bit clock is 10 to 12.5 GHz (sub 100ps clock periods).
>>>
>>> I remember well the "good old days" where 5 micron CMOS ASICS had a
>> hard time doing DS-1 rates, and gallium arsenide was going to kill off
>> CMOS at DS-3 and above.
>>>
>>> -Dave
>>>
>>>
>>> On March 5, 2016 6:24:30 AM PST, Magnus Danielson
>> <magnus at rubidium.dyndns.org> wrote:
>>>> As I have read this thread, I have been waiting for this to show up.
>>>> We use this technique a lot and it is fairly simple anyway.
>>>>
>>>> It is also an important technique for bit-error testing, and not
>> only
>>>> for scrambling.
>>>>
>>>> However, what technique makes the most efficient code for a
>> processor
>>>> is
>>>> a different matter than if you do it in hardware as we usually do.
>>>>
>>>> Originally I thought the matter was to get the sequence length to
>>>> shorten to a particular number of symbols, say a power of 2 length.
>> A
>>>> technique being used is to shorten a maximum length sequence.
>>>>
>>>> If you have X bits state, you can produce Y output bits from that X
>>>> bits
>>>> and then produce the next X bits. By taking the polynomial for
>>>> producing
>>>> 1 bit, then shift 1 bit and produce the next bit etc. after doing
>> this
>>>> for Y bits you have the output of Y bits and the X bits output
>> state.
>>>> It
>>>> is relatively simple, it's just as we jumped Y rather than 1 bits in
>>>> the
>>>> sequence and directly predict that. It's a bit of work to build the
>> new
>>>>
>>>> update polynomial, but paper and pen is a good way to get started on
>> a
>>>> small polynomial, and once the exercise have been done you realize
>> how
>>>> you can do it for any size and even automate the polynomial length.
>>>>
>>>> Cheers,
>>>> Magnus
>>>>
>>>> On 03/04/2016 08:07 PM, Dave Manley wrote:
>>>>> It hasn't been mentioned, but the LFSR implementation can be done
>> so
>>>> that it generates multiple bits per update, not just a single bit.
>>>> This is commonly done in telecom/ networking descramblers which
>> operate
>>>> on a multi-bit serdes output.
>>>>>
>>>>> -Dave
>>>>>
>>>
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