[sdiy] STM32 vs WM8731

[Eric Brombaugh]

You may be mistaking the internal clock to the I2S peripheral of the 
STM32 with the MCK output. They're not the same thing.

Eric

On 02/17/2016 11:53 AM, Rob Spencer wrote:
> For some reason STM32CubeMx doesn’t seem to like anything lower that
> 1000x the sample rate…
>
> https://www.dropbox.com/s/a22vmj9t1szljzr/Screenshot%202016-02-17%2018.50.11.png?dl=0
>
> https://www.dropbox.com/s/mr0a1erzbs1tmo6/Screenshot%202016-02-17%2018.51.15.png?dl=0
>
> Rob Spencer
> gmsn.co.uk
> 07590 267835
>
>
>
>
> On 17/02/2016 18:14, "Synth-diy on behalf of Eric Brombaugh"
> <synth-diy-bounces at dropmix.xs4all.nl
> <mailto:synth-diy-bounces at dropmix.xs4all.nl> on behalf of
> ebrombaugh1 at cox.net <mailto:ebrombaugh1 at cox.net>> wrote:
>
>     The I2S master clock output from the STM32 will only be present when
>     the
>     I2S port is active. You need to have the peripheral fully configured
>     and
>     DMA running before you see any traffic on the I2S signals.
>
>     I generally wait until after the I2S port is up and running before
>     trying to issue commands on the I2C control port. I'm not 100% certain
>     that this is necessary in all cases, but the WM8731 does some adaptive
>     configuration based on the command setup and the measurements it
>     does of
>     the incoming I2S clock ratios, so it's best to have all the information
>     present when you command it.
>
>     The frequency and hence visibility of the MCK signal depends on what
>     oversampling ratio you've chosen. For a typical 48ksps sample rate with
>     a 256x oversample ratio the MCK should be about 12.288MHz which should
>     be well within your equipment's capability. You can run the codec at
>     64x
>     and 128x as well, so it's possible you could get an MCK of less than
>     20MHz even if you're running at 192ksps.
>
>     Eric
>
>     On 02/17/2016 11:00 AM, Rob Spencer wrote:
>
>         I think I’m getting to the crux of the issue.
>
>         Am I right in thinking I2S MCK is only active when sending data
>         across I2S? So if it’s in DMA mode, it will be active.
>
>         And without MCK or it’s own clock, the CODEC can’t ACK the I2C
>         traffic?
>
>         I’m also working on the assumption that I can’t measure MCK as
>         it’s over the 20MHz limit of my scope and logic analyser.
>
>
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