[sdiy] In praise of the ATM STM32F303

[rsdio at audiobanshee.com]

On Feb 12, 2016, at 9:45 AM, rburnett at richieburnett.co.uk wrote:
> The ability to "asynchronously" clock the DMA module is very neat.  I make extensive use of DMA for ADC, DAC, UART, CRC, etc, on dsPICs, but have never seen the option of an external clock before.  Perfect for arbitrary waveform generation with true variable sample rate.
Typically, digital PLL circuits can create any clock frequency you might need, but there is a bit too much jitter for audio purposes. Some chips have on-board analog PLL circuits for smoother audio clocks to solve this problem. Analog PLL can come in handy for other things like USB.

I have not looked at the STM32F303, but if it's lacking an analog PLL then this external clock is surely for allowing an external clock of higher quality - or maybe just to synchronize with something like a SPDIF input. Even if the STM32F303 has analog PLL, there can be good reasons to make it easy for external audio clocking.


> (I suppose the DAC update instants are synchronised to the CPU clock internally by the DMA module's arbitration circuitry to interleave the DMA reads with normal processor memory accesses, unless the chip has dual-port memory specially for DMA like the dsPIC.  Either way the jitter from this synchronisation shouldn't cause too much aliasing unless you take the clocking speed up into the hundreds of kHz.  Then the jitter from synchronising edges of say a 500kHz clock with the CPU clock might start to be audible.)
Even if the jitter is low enough to avoid objectionable aliasing, it still introduces noise and distortion in the converted signal. If the DMA to DAC flow has one sample of latency, then it would be possible for conversions to be precisely locked to the external clock despite jitter in the memory access itself. All that's needed is some place to stash one sample (per channel), such that each clock converts the previously-fetched sample before triggering the fetch of the next sample. That way, memory access can be delayed by arbitration without introducing jitter in the converter output.

I've worked with DAC chips that have this one-sample latency built in, such as the Texas Instruments THS5671A. That's a 14-bit converter capable of 125 Msps. Each clock that it sees will convert whatever value was previously stored, and then latch in a new value from the parallel input pins. As long as the clock is jitter free, the output will be too, and the system has almost a whole clock period to fetch the next sample value and hold it on the input pins for the next clock transition.

Again, I haven't looked at the STM32F303 data sheets, but if their DAC peripherals have this sort of feature, then any memory bus latency won't introduce jitter relative to the external clock.

You are correct, though, that external clocking must be adapted to the internal bus clock unless they allow completely interruptible bus cycles with restart (in case the DAC DMA happens in the middle of another access). It's most likely that they have bus arbitration that delays the access until it fits.


> I'm sure it will have lots of uses in things like digitally controlled arbitrary waveform generators and the like.
That's certainly possible, but the external clock is also highly useful for audiophile waveform reproduction with reduced jitter, assuming the necessary design components are present.

Brian Willoughby
Sound Consulting