[sdiy] Digital delay memory

[Eric Brombaugh]

On 04/27/2016 09:22 AM, Richie Burnett wrote:
> Tom and Eric, have you looked at the 23LC1024 SPI SRAM chip to
> supplement on-board delay memory?  (1MBit external static-RAM in 8-pin
> SOIC/TSSOP package for a couple of bucks.  A couple of seconds delay at
> 32kHz/16bit.)

I played around with the earlier 256kbit version a few years ago. Never 
got too deep into it though - certainly not to the point of look-ahead 
paging as you mentioned. Seems like an interesting idea.

> Also had good success with old computer DRAM simms for *loooooooong*
> audio delay.  (Made a profanity delay for broadcast applications.)  All
> the RAS/CAS/refresh stuff isn't really that hard to implement for the
> old page-mode or EDO chips, and you could pick them up cheap on ebay.
> It requires more I/O lines than SPI, but not as much as parallel SRAM.
> Haven't tried interfacing to modern Synchronous DRAM though.  It looks a
> lot more complicated!?

I've not worked with those at all, but there do seem to be a few designs 
out there that use modern fast MCUs to talk to old DRAM. Sandrine over 
on the MW DIY forum has a design that uses a PIC to do the DRAM 
addressing with an AVR as a supervisor.

https://www.muffwiggler.com/forum/viewtopic.php?t=150299

A unique approach - definitely "outside the box".

I've built systems with STM32F42x processors and more modern SDRAMs that 
support up to 64MB for delay buffers. It's really pretty easy to do - 
the layout isn't too critical and the software setup was simple. I had 
no problems with it at all. It fits on a fairly compact 4-layer PCB 
along with a good codec chip.

Eric