[sdiy] 1-bit ADC for audio/audio delay
David Moylan
dave at westphila.net
Tue Apr 12 23:55:23 CEST 2016
There are some issues with sigma delta to remember:
On a 1 bit converter it takes a whole lot of oversampling to achieve a
high equivalent bit depth. If I recall a single order integrator gives
optimum 1.5 bits for every doubling of frequency, second order is 2.5.
Somebody google that for me... :)
The RC filter in the feedback path determines the transition frequency
of the noise shaping. The thought then would be that you want that
transition frequency to be as high as possible so that the noise is
shaped to boost frequencies way beyond the cutoff frequency of the
reconstruction filter but there are other concerns. If the RC time
constant is too small you can saturate the filter. I saw a reference
that said optimum RC (for a true integrator) is 1/RC = f, where f is the
sampling frequency, but was unable to see the original source which is
an expensive text book:
Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance
Limits and Robust Implementations, Gerfers & Ortmanns
In my experiments I felt like I was still getting saturation with those
values and increased the capacitor value a bit, and also degraded the
maximum gain of my integrator.
I don't believe the reconstruction filter needs to match the values of
the loop filter. The loop filter should be optimized with the previous
concerns in mind. The reconstruction filter should have the lowest
possible cutoff that suits your desired signal bandwidth.
HTH
Dave Moylan
On 04/11/2016 06:12 PM, Tom Wiltshire wrote:
> One further thing: I couldn't get the RC values provided in the article to work at all. They suggest "The output of the comparator (Point B) is integrated by Rx, Cx (typically 10 Ω, and 0.01 µF)" but I finished up using 100K and 4n7 to get a better result. This is so different that something fishy is going on.
>
> Tom
>
> On 11 Apr 2016, at 22:59, Tom Wiltshire <tom at electricdruid.net> wrote:
>
>> Hi All,
>>
>> I've been experimenting with the following circuit that I found online:
>>
>> http://www.electricdruid.net/images/DeltaSigmaADC.png
>>
>> Original article is:
>>
>> http://electronicdesign.com/analog/low-cost-audio-delay-line-uses-1-bit-adc
>>
>> Everyone likes a simple audio delay, right? And you can't get much simpler for a digital delay than that, so I thought it'd be worth playing with. Note that the image in the original article has an error and takes the feedback from the wrong place, after the comparator instead of after the latch. My image is corrected.
>>
>> Now, the circuit works well enough, but it doesn't work as well as I'd expected. For now, I've got no shift register. I'm just doing the ADC, then feeding the bits out again so I can compare input and output signals for quality. I've done lots of experiments with PWM audio output, and I've got better results than I'm getting out of this. And this *should* work better than PWM, since the "PDM" output it produces should have less jitter than a PWM output would.
>>
>> In practice, it's quiet with no signal going in (what would be the worst case for PWM - the midpoint voltage) but when it gets a signal, there's a substantial amount of background white(ish) noise. Now, I understand that it's never going to be hi-fi (that's not the point) but I don't understand why I should get more noise with a signal than without.
>>
>> I've also been reading around Delta-Sigma convertors in general (of which this is a basic example) and I've noticed that this circuit arranges the typical components (comparator, integrator, differential amp) in a different order than many.
>>
>> Would swapping the passive RC filter for a active 2-pole filter improve things? Would a op-amp integrator stage help? (it'd be more linear at the extremes for starters..) These experiments are my probable next steps. And how would I go about converting such a Delta-Sigma modulator into a second-order modulator in the style of:
>>
>> http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html
>>
>> (This is one of the examples that uses the same bits, but in a different order).
>>
>> Any pointers to further information appreciated, or clues as to what I might be doing wrong.
>>
>> Thanks,
>> Tom
>>
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