[sdiy] 1-bit ADC for audio/audio delay

[Tom Wiltshire]

Haha! It was thinking about the PT2399 that set me off in this direction in the first place! I blame that chip for many, many things!

On 11 Apr 2016, at 23:35, Jacob Watters <jacobwatters at gmail.com> wrote:

> I think the pt2399 works in a similar way. Try checking its datasheet to point you in the right direction.
> 
> On Monday, 11 April 2016, Eric Brombaugh <ebrombaugh1 at cox.net> wrote:
> Tom,
> 
> Looks like you're on the same path as Batz Goodfortune:
> 
> http://www.all-electric.com/b&c.html
> 
> I fooled around with that circuit many years ago - even updated it with a CPLD for the DRAM address generator.
> 
> The main trouble is that it's only a 1st-order sigma-delta so it's not going to have super great performance. I suppose you could try building a higher-order sigma-delta, but those get pretty complicated and then you can start having stability issues. Performance of the 1st-order circuit will improve somewhat as you raise the oversampling ratio, but that's expensive since it requires longer shift registers for the same delay.
> 
> You might have better luck using an SACD style codec instead of a home-made S/D. SACD codecs output the raw bitstream that hasn't been converted to PCM and incorporate higher-order converters.
> 
> Eric
> 
> On 04/11/2016 02:59 PM, Tom Wiltshire wrote:
> Hi All,
> 
> I've been experimenting with the following circuit that I found online:
> 
>         http://www.electricdruid.net/images/DeltaSigmaADC.png
> 
> Original article is:
> 
>         http://electronicdesign.com/analog/low-cost-audio-delay-line-uses-1-bit-adc
> 
> Everyone likes a simple audio delay, right? And you can't get much simpler for a digital delay than that, so I thought it'd be worth playing with. Note that the image in the original article has an error and takes the feedback from the wrong place, after the comparator instead of after the latch. My image is corrected.
> 
> Now, the circuit works well enough, but it doesn't work as well as I'd expected. For now, I've got no shift register. I'm just doing the ADC, then feeding the bits out again so I can compare input and output signals for quality. I've done lots of experiments with PWM audio output, and I've got better results than I'm getting out of this. And this *should* work better than PWM, since the "PDM" output it produces should have less jitter than a PWM output would.
> 
> In practice, it's quiet with no signal going in (what would be the worst case for PWM - the midpoint voltage) but when it gets a signal, there's a substantial amount of background white(ish) noise. Now, I understand that it's never going to be hi-fi (that's not the point) but I don't understand why I should get more noise with a signal than without.
> 
> I've also been reading around Delta-Sigma convertors in general (of which this is a basic example) and I've noticed that this circuit arranges the typical components (comparator, integrator, differential amp) in a different order than many.
> 
> Would swapping the passive RC filter for a active 2-pole filter improve things? Would a op-amp integrator stage help? (it'd be more linear at the extremes for starters..) These experiments are my probable next steps. And how would I go about converting such a Delta-Sigma modulator into a second-order modulator in the style of:
> 
> http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html
> 
> (This is one of the examples that uses the same bits, but in a different order).
> 
> Any pointers to further information appreciated, or clues as to what I might be doing wrong.
> 
> Thanks,
> Tom
> 
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