[sdiy] Eagle footprints

[rsdio at audiobanshee.com]

Cadsoft does not create all of the devices in the provided library. In fact, there are additional libraries available for download from their site. This explains the wide variety of quality and style. Some are probably so old that they existed before Cadsoft bought the rights to Eagle.

I maintain my own private library of parts, symbols, and packages, and then copy selected devices from the other libraries as needed. This way, once I have an SOIC marking that I like, I can easily reuse it for new SOIC parts. Also, I know that all the devices in my personal library have been vetted on previous fabrications. Over time, the design process gets quicker if you're using your own library. The only trouble is that when I work for hire, I need to provide the library when I'm paid for the layout, and that means I have to create a third-party library for the client. Eagle has handy 'copy' commands for duplicating devices across library files.

There's probably no reason to worry about silkscreen over SMD pads, because even the cheapest fab houses will automatically remove them. The bigger reason, in my opinion, to remove them is because they don't do anybody any good if they're never printed.

I'd recommend placing at least a 'dot' or something that is visible after the SMD chip has been placed. You wouldn't believe how many times the CAD file will get the orientation 180 degrees off. I tend to match the markings on the chip itself with my silk, so that it's obvious. Under the chip, you can put more extensive markings (unless there is a large ground pad for heat dissipation).

Brian Willoughby
Sound Consulting


On Nov 20, 2015, at 12:54 PM, "Richie Burnett" <rburnett at richieburnett.co.uk> wrote:
>> You could change the settings of the gerber cam to also include tdocu, that would be a quick fix.
> 
> Thanks Jarno.  I could do that.  I tried it, but it results in many instances of silkscreen printing over SMD pads which I don't like.  Most board houses I've used crop the silkscreen layer against the resist layer before fabrication to prevent ink on pads, but I'd rather avoid intentionally creating artwork that way.
> 
> From the replies I've been getting it sounds like it's a good idea to just edit the footprints to at least include some orientation mark on the tPlace layer (21)
> 
> -Richie,
> 
> 
> ------ Origineel bericht------
> Van: Richie Burnett
> 
> A question for the Cadsoft Eagle gurus…
> 
> Just finishing off a PCB here with Eagle and noticed that all of the SOIC devices have no component outlines or orientation markings on the silkscreen layer, only tDocu which can be printed off as documentation to aid in assembly but doesn't end up in the silkscreen Gerber file. All other semi packages used on this board like TSSOP, TQFP, SOT23 etc, have at least partial outlines and orientation markings on the silkscreen layer, often with more extensive detail on the tDocu layer. I'm happy with these.
> 
> Is there some reason for this? Did Cadsoft just forget to put orientation markings in the SOIC package footprints in their libraries, or is there some rule of PCB design somewhere that says there shouldn't be silkscreen ink under SOIC devices? Does it interfere with the correct seating of SOIC packages during reflow, or can I just add silkscreen orientation marks under the device body to the footprints that I'm using to aid? I can understand not putting silkscreen orientation marks under QFNs that are planar on the bottom and pretty much have to be put on by machine anyway, but some orientation marks on SOIC's would really help with manual placement.
> 
> I realise that any marking underneath the ICs will be covered after fitting and make checking device orientation difficult, but I'd rather not put orientation marks outside the perimeter of the part as component packing density is very high!
> 
> I'm interested to hear any thoughts on this,-Richie,