[sdiy] Eagle footprints

[Richie Burnett]

> You could change the settings of the gerber cam to also include tdocu, 
> that would be a quick fix.

Thanks Jarno.  I could do that.  I tried it, but it results in many 
instances of silkscreen printing over SMD pads which I don't like.  Most 
board houses I've used crop the silkscreen layer against the resist layer 
before fabrication to prevent ink on pads, but I'd rather avoid 
intentionally creating artwork that way.

>From the replies I've been getting it sounds like it's a good idea to just 
edit the footprints to at least include some orientation mark on the tPlace 
layer (21)

-Richie,


-----Original Message----- 
From: jarno.verhoeven at ziggo.nl
Sent: Friday, November 20, 2015 8:38 PM
To: synth-diy
Subject: Re: [sdiy] Eagle footprints



Checked my board stash, and there are a few boards which do have the 
outline, and a few that don't. It seems the tl072 component doesn't have the 
outlines, but a board with some smt tl074's and cmos does have outlines. 
(and I use lbr's that eagle came with)

You could change the settings of the gerber cam to also include tdocu, that 
would be a quick fix.

Best regards,

Jarno.






------ Origineel bericht------

Van: Richie Burnett

Datum: vr, 20 nov. 2015 21:18

Naar: synth-diy;

CC:

Onderwerp:[sdiy] Eagle footprints




A question for the Cadsoft Eagle gurus...Just finishing off a PCB here with 
Eagle and noticed that all of the SOIC devices have no component outlines or 
orientation markings on the silkscreen layer, only tDocu which can be 
printed off as documentation to aid in assembly but doesn't end up in the 
silkscreen Gerber file. All other semi packages used on this board like 
TSSOP, TQFP, SOT23 etc, have at least partial outlines and orientation 
markings on the silkscreen layer, often with more extensive detail on the 
tDocu layer. I'm happy with these.Is there some reason for this? Did Cadsoft 
just forget to put orientation markings in the SOIC package footprints in 
their libraries, or is there some rule of PCB design somewhere that says 
there shouldn't be silkscreen ink under SOIC devices? Does it interfere with 
the correct seating of SOIC packages during reflow, or can I just add 
silkscreen orientation marks under the device body to the footprints that 
I'm using to aid? I can understand not putting silkscreen orientation marks 
under QFNs that are planar on the bottom and pretty much have to be put on 
by machine anyway, but some orientation marks on SOIC's would really help 
with manual placement.I realise that any marking underneath the ICs will be 
covered after fitting and make checking device orientation difficult, but 
I'd rather not put orientation marks outside the perimeter of the part as 
component packing density is very high!I'm interested to hear any thoughts 
on this,-Richie, __________ _____________________________________Synth-diy 
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listSynth-diy at dropmix.xs4all.nlhttp://dropmix.xs4all.nl/mailman/listinfo/synth-diy





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