[sdiy] 4046 VCO overclocking a PIC

Tim Ressel timr at circuitabbey.com
Sat Aug 29 00:32:21 CEST 2015


The dsPIC33FJ128GP allows for the PLL to be bypassed.

--tr


On 8/28/2015 3:00 PM, Paul Schreiber wrote:
> Most dsPICs have a PLL lock range of only 4MHz to 16MHz input clock range.
>
> Paul S.
>
>
> --- tom at electricdruid.net wrote:
>
> From: Tom Wiltshire <tom at electricdruid.net>
> To: Richie Burnett <rburnett at richieburnett.co.uk>
> Cc: synth DIY <Synth-diy at synth-diy.org>
> Subject: Re: [sdiy] 4046 VCO overclocking a PIC
> Date: Fri, 28 Aug 2015 22:17:28 +0100
>
>
>> Tom, are the pics with PLL clock multiplication happy with the input frequency going right down to DC?  I know the VCO in  the Dspic's PLL has quite a small locking range. Like just one octave if I remember correctly :-(
> I don't know. I haven't seen anything to suggest that the PLL can't cope, but it's a good question. If you really want to go slowly, I guess you don;t need the PLL anyway, so there wouldn't be much point. But you're right, for my current application it might provide a lower limit on how far down the clock can go before the PLL loses its lock.
>
>> You told me about a pic with an NCO module built in once. Have you done any experiments with that?
> I've done quite a few, but nothing to do with clocking the chip. I've got a flanger clock design done using it. It uses the NCO controlled by a software LFO to generate a modulated BBD clock suitable for a flanger from a single 8-pin chip. It replaces the MN3102, but you don't need at LFO as well, and you can have loads of extra waveforms, and top-down or bottom-up flanging and so forth. Reduces a flanger circuit to something reasonable, in short.
>
> Tom
>
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-- 
--Tim Ressel
Circuit Abbey
timr at circuitabbey.com



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