[sdiy] 4051 spikes

[m brandenberg]

On Sat, 25 Apr 2015, florian anwander wrote:

> Is this normal? Is it caused by the breadboarding setup?

It looks like you are:
   -  Clocking the address pins
   -  Tying common pin to vdd via 100K
   -  Floating IO pins (0-6)
   -  Measuring IO pin 7 (b111)
   -  Getting glitches at b011->b100 and b101->b110

This looks like maybe the 1-of-8 circuit isn't a safe
("no-glitch") design but rather a more minimal one with
non-overlapping domains in the Karnaugh map.  The decay
time constant might be the leakage of the IO 7 pad
driver draining the C of the probe + stray C in the
breakboard.

Put a reasonable resistor between pin 4 and probe
and it'll clean up.  Or use the inhibit during clock
transitions.

m

--
Monty Brandenberg