[sdiy] DAC/REF Data sheet / Dev board R question

[Justin Owen]

Hi Neil,

I did actually read that very paragraph - that's what got me asking! :)

So... is the diagram I linked in the OP putting that 1.5R in series to show the maximum ESR for the cap?

The diagram you've referenced in the REF5025 datasheet doesn't have the R in series - it just mentions the requirement for a cap with an ESR of <1.5R.

That makes sense and the cap I'm using has a stated ESR of 0.85R - which should be fine...

...or am I still missing something?



The cap I'm using has an ESR of 
>> http://www.sdiy.org/juz/REF_DAC_01.png

If you read the REF5025 datasheet (yeah, I know, who bothers reading
datasheets on a Saturday afternoon, eh?) you'll find this text:

"A 1-μF to 50-μF, low-ESR output capacitor (CL) must be connected from
VOUT to GND. The ESR value should be less than or equal to 1.5 Ω. The
ESR minimizes gain peaking of the internal 1.2-V reference and thus
reduces noise at the VOUT pin."

Since we can reasonably assume that the folks who wrote the document
knew what they're talking about, or at the very least had access to
the folks who designed the chips in the first place, I think it wise
to carefully study the example circuit, since it would have been
designed to demonstrate the parts at their best (that evaluation
module is a marketing tool, so it needs to do battle with devices from
competitors).

Neil
--
http://www.njohnson.co.uk