[sdiy] Freescale Kinetis K2 Arm Cortex M4: 120MHz, FPU & I2S DAC/ADC interface
nvawter
nvawter at media.mit.edu
Thu Sep 11 16:23:28 CEST 2014
> I don't know what the typical instruction cycle time of the Cortex M4
> is, but if the MIPS and FLOPS is anything like the 120MHz clock
> frequency, they would be able to do a great deal of work per audio
> sample cycle.
Kinetis vs. ST Cortex M4 is an area of interest for me. The stm32f4 has
been a favorite chip of
mine for the last year and a half. I've been documenting tons of
information
and demos with a slant toward music on it on my little website:
http://diydsp.com/livesite/pages/stm32f4
I've also developed a credit-card-sized Music-Optimized Breakout Board
(MOBB) for it. It works great in numerous
instruments I've built, but could still be improved. If anyone is
interested in helping me with the DAC output filter
or the analog noise reduction or getting one, please click this link to
see my MOBB from my google drive
(you don't need a google account):
https://drive.google.com/folderview?id=0B27wuPBwl_tbSGdkcGhtR1RiLVE&usp=sharing
Now onto the instruction times of the Cortex M4F!!
(F = M4 w/ FPU, but is not consistently used)
Here are the highlights for the FPU, 32-bit floats:
Cycles, Operation
1, abs
1, add/sub
1, compare
1, convert int<->fixed<->float<->half precision
14, divide (you knew this would suck!)
1, multiply (heck, ya!)
3, mac (multiply and accumulate/subtract)
3, fused multiply and add
14, square root (a nice bonus)
sin/cos/tan/etc not implemented
There is also a 1 cycle load/store time associated with moving the
values to/fro FPU registers. (so you
want to keep values hanging out in the 32x 32-bit FPU register file if
at all possible.)
If anyone is unfamiliar with fused multiply and add, it increases
accuracy over doing a separate multiply and add.
Those numbers are from this doc which has the M4F cycle times:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/CHDDIGAC.html
iiuc, several vendors such as ST put an "ARD" aka instruction cache
in front for the slow flash so they can clock the core at up to 168 MHz.
(some folks have overclocked to 250!)
Many parts running at e.g. 72 MHz were really just limited by the flash
instruction fetch iiuc. I'm glad to see Kinetis reach 120 MHz. Do you
know if they're
using a cache or if the core is @120 MHz. Also, I couldn't find the
specs on the A/D and D/A
on the Kinetis chips.
-Noah
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