[sdiy] High frequency VCO designs

[rburnett at richieburnett.co.uk]

> Why not implement the DDS in the PIC? The PIC only has to have an
> interrupt, increment a register, and toggle an output when it
> overflows so you can set the interrupt rate to be pretty high.

You get period jitter if the DDS generates a square or pulse waveform 
directly from it's phase accumulator.  This is because the transitions 
of the pulse are forced to line up with the DDS master clocking edges.  
(It is actually the same phenomenon as what we would call aliasing in 
the frequency domain, and occurs because the pulse waveform has an 
infinite spectrum but it is being generated at a finite sample rate.)

Only a sinewave synthesised by DDS is free from aliasing.  You can then 
smooth this with a reconstruction filter and put it through a comparator 
to get a square or pulse waveform that is free from aliasing.  (The 
edges on this jitter-free pulse output can and do happen in between the 
transitions of the DDS master clock.)  This is how high quality DDS 
based function generators like Agilent's 33220A work.

-Richie,