[sdiy] High frequency VCO designs

[rburnett at richieburnett.co.uk]

The problem with RF VCO's is that the linearity and temperature drift 
may be quite poor.  Certainly by music standards where you want decent 
pitch conformity over some range of semitones.

Radio Frequency VCOs usually end up being placed inside the feedback 
loop of a PLL, so within reason linearity and drift are not important 
design parameters for the VCO.  (When it's inside the PLL the integral 
action of the control loop forces out the frequency error that you would 
get if the VCO was operated open loop on it's own.)

If your voltage control is only to apply vibrato then I think you'll be 
fine, but if you try to achieve any sort of tracking of a musical scale 
you might be dissapointed.  Then you're left with three options:

1. Try to compensate for the non-linearity and drift of the VCO.  Very 
messy.

2. Put the VCO inside a PLL, but this might be tricky to get 
sufficiently fine frequency resolution, and quick response time, and 
good stability.

3. Abandon the PLL idea and go with a DDS solution.

If I found myself needing to go down the route of buidling a PLL that 
requires dividers to be programmed digitally, I would switch to a DDS 
based oscillator and program that digitally instead.  In my option the 
modern DDS is a much quicker and easier solution.  You get ultra-fine 
frequency resolution, lightening fast frequency changes, perfect 
linearity, and very low drift.  All this with none of the cold-sweat 
inducing control-loop challanges inherent with a Phase Locked Loop 
design.

I'd vote DDS all the way, but a VCO it isn't unfortunately.

-Richie,


On 2014-09-23 11:15, Tom Wiltshire wrote:
> Because a PIC/uP needs a faster clock/more instructions to emulate a
> bit of old CMOS than the original CMOS needed. 20MHz is the upper
> limit for the standard 16F chips. 32MHz is the upper limit for the
> 16F1xxx enhanced chips. Somewhere around there is "chip clocked at
> full power with vibrato applied". So maybe 20-32MHz is enough.
> Even with the increased clock speed, I think you're unlikely to be
> able to do better than the typical 9-bit divider sequence (/478 to
> /239). And anyway, I wouldn't want to, since the errors in that
> sequence are part of the sound I'd be trying to emulate.
> 
> Tom
> 
> On 23 Sep 2014, at 07:01, Tim Ressel <timr at circuitabbey.com> wrote:
> 
>> Um, why 20-40MHz? The 50240 TOG uses 1/10 that. At 2 MHz the venerable 
>> 4046 will do the trick.
>> 
>> Tim Ressel
>> Circuit Abbey
>> 503-750-9331
>> timr at circuitabbey.com
>> 
>> 
>> 
>> ----- Original Message -----
>> From: Tom Wiltshire <tom at electricdruid.net>
>> To: synthdiy diy <synth-diy at dropmix.xs4all.nl>
>> Cc:
>> Sent: Monday, September 22, 2014 2:01 PM
>> Subject: [sdiy] High frequency VCO designs
>> 
>> Hi All,
>> 
>> What contemporary VCO designs are there that can cope with frequencies 
>> between 20-40MHz?
>> 
>> There were several synth designs based on top-octave-dividers that 
>> used a high frequency VCO to clock the divider (PolyMoog, for one 
>> example). It occurred to me (and I'm not the first) that whilst you 
>> can't copy aTOG chip in a PIC, you can adequately copy a single output 
>> of a clock chip and it's associated divider. This is closer to the 
>> older 12-separate-oscillators-plus-dividers scheme. But that's fine, 
>> better even. The important thing is to get some voltage control in 
>> there by using a VCO for the uP clock.
>> 
>> So, VC-clocks for a PIC? Any ideas?
>> 
>> Thanks,
>> Tom
>> 
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