[sdiy] High frequency VCO designs

[Tom Wiltshire]

Because a PIC/uP needs a faster clock/more instructions to emulate a bit of old CMOS than the original CMOS needed. 20MHz is the upper  limit for the standard 16F chips. 32MHz is the upper limit for the 16F1xxx enhanced chips. Somewhere around there is "chip clocked at full power with vibrato applied". So maybe 20-32MHz is enough.
Even with the increased clock speed, I think you're unlikely to be able to do better than the typical 9-bit divider sequence (/478 to /239). And anyway, I wouldn't want to, since the errors in that sequence are part of the sound I'd be trying to emulate.

Tom

On 23 Sep 2014, at 07:01, Tim Ressel <timr at circuitabbey.com> wrote:

> Um, why 20-40MHz? The 50240 TOG uses 1/10 that. At 2 MHz the venerable 4046 will do the trick.
> 
> Tim Ressel
> Circuit Abbey
> 503-750-9331
> timr at circuitabbey.com
> 
> 
> 
> ----- Original Message -----
> From: Tom Wiltshire <tom at electricdruid.net>
> To: synthdiy diy <synth-diy at dropmix.xs4all.nl>
> Cc: 
> Sent: Monday, September 22, 2014 2:01 PM
> Subject: [sdiy] High frequency VCO designs
> 
> Hi All,
> 
> What contemporary VCO designs are there that can cope with frequencies between 20-40MHz?
> 
> There were several synth designs based on top-octave-dividers that used a high frequency VCO to clock the divider (PolyMoog, for one example). It occurred to me (and I'm not the first) that whilst you can't copy aTOG chip in a PIC, you can adequately copy a single output of a clock chip and it's associated divider. This is closer to the older 12-separate-oscillators-plus-dividers scheme. But that's fine, better even. The important thing is to get some voltage control in there by using a VCO for the uP clock.
> 
> So, VC-clocks for a PIC? Any ideas?
> 
> Thanks,
> Tom
> 
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