[sdiy] Freescale Kinetis K2 Arm Cortex M4: 120MHz, FPU & I2S DAC/ADC interface

[Terry Shultz]

Hi Robin,

I see that Freescale have Kinetis “K” Series in various flavors up to 150 MHz. and mention on their web page 180 MHz parts.

These devices ave SSi ports which are I2S and have Network/TDM and single ended I2S support.

These SSI ports are subsets of the DSP5637x series of Audio DSP and i.MX series.

I am betting that Ti and others are very similar.

What point is a ST superior over Freescale , Ti, etc.?

What we need is a Matrix of all the similar devices based on Memory, I/O. Speed, Cost, and footprint.

It not so obvious that one Cortex M4 is better than another. 

I have a great deal of experience with the Freescale devices as a previous employee of Freescale/ Motorola for almost 28 years.

I have a great deal of ARM based hardware from Freescale competitors and it all blurs a bit on who is best.

App notes and low-cost boards are not a sign of superior performance. I like to see us put our heads together and build a superior
Arduino Audio platform that support more than stereo I/O.

Contact me off line if you wish to collaborate on a call . I would like to see your point of view before I go into a online dialog.

best regards,

Terry Shultz

thx1138 at earthlink.net
On Sep 11, 2014, at 9:33 PM, Robin Whittle <rw at firstpr.com.au> wrote:

> Hi Noah,
> 
> Thanks for this information.  This has been a most interesting discussion.
> 
> The ST chips go to 180MHz and have dual I2S interfaces, including in
> LQFP-100 packages.  For instance:
> 
> http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1789
> 
> with 256kB RAM and 1024kB or 2048kB FLASH.  This is superior to the
> Freescale and Infineon chips I mentioned in earlier messages.
> 
> I tried accessing your page:
> 
> https://drive.google.com/folderview?id=0B27wuPBwl_tbSGdkcGhtR1RiLVE&usp=sharing
> 
> and even with a Google login, I had to request permission to view it,
> which will supposedly come by email.
> 
> I haven't yet looked at the TI DSPs:
> 
> http://www.ti.com/lsds/ti/dsp/overview.page
> 
> I think TI's Arm Cortex M4 chips do not have either FPUs or I2S
> interfaces.
> 
> 
> - Robin
> 
> 
> 
> 
> On 2014/09/12 12:23 AM, nvawter wrote:
>> 
>>> I don't know what the typical instruction cycle time of the Cortex M4
>>> is, but if the MIPS and FLOPS is anything like the 120MHz clock
>>> frequency, they would be able to do a great deal of work per audio
>>> sample cycle.
>> 
>> 
>> Kinetis vs. ST Cortex M4 is an area of interest for me.  The stm32f4 has
>> been a favorite chip of
>> mine for the last year and a half.  I've been documenting tons of
>> information
>> and demos with a slant toward music on it on my little website: 
>> http://diydsp.com/livesite/pages/stm32f4
>> 
>> I've also developed a credit-card-sized Music-Optimized Breakout Board
>> (MOBB) for it.  It works great in numerous
>> instruments I've built, but could still be improved.  If anyone is
>> interested in helping me with the DAC output filter
>> or the analog noise reduction or getting one, please click this link to
>> see my MOBB from my google drive
>> (you don't need a google account):
>> https://drive.google.com/folderview?id=0B27wuPBwl_tbSGdkcGhtR1RiLVE&usp=sharing
>> 
>> 
>> Now onto the instruction times of the Cortex M4F!!
>> (F = M4 w/ FPU, but is not consistently used)
>> 
>> Here are the highlights for the FPU, 32-bit floats:
>> 
>> Cycles, Operation
>> 1, abs
>> 1, add/sub
>> 1, compare
>> 1, convert int<->fixed<->float<->half precision
>> 14, divide (you knew this would suck!)
>> 1, multiply (heck, ya!)
>> 3, mac (multiply and accumulate/subtract)
>> 3, fused multiply and add
>> 14, square root (a nice bonus)
>> sin/cos/tan/etc not implemented
>> There is also a 1 cycle load/store time associated with moving the
>> values to/fro FPU registers.  (so you
>> want to keep values hanging out in the 32x 32-bit FPU register file if
>> at all possible.)
>> If anyone is unfamiliar with fused multiply and add, it increases
>> accuracy over doing a separate multiply and add.
>> 
>> Those numbers are from this doc which has the M4F cycle times:
>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/CHDDIGAC.html
>> 
>> 
>> 
>> iiuc, several vendors such as ST put an "ARD" aka instruction cache
>> in front for the slow flash so they can clock the core at up to 168 MHz.
>> (some folks have overclocked to 250!)
>> Many parts running at e.g. 72 MHz were really just limited by the flash
>> instruction fetch iiuc.  I'm glad to see Kinetis reach 120 MHz.  Do you
>> know if they're
>> using a cache or if the core is @120 MHz.  Also, I couldn't find the
>> specs on the A/D and D/A
>> on the Kinetis chips.
>> 
>> -Noah
>> 
>> 
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