[sdiy] Analog envelope generator offset

[Ian Fritz]

Hi Tom --

Good to see you going beyond Spice to try some analysis.

Assume the U1b (+) input (Gate signal) has just switched from +5V to 
0V.  Since negative feedback is present, the (-) input also goes to 
0V.  This is one of the "golden rules" of ideal opamps.  To satisfy this 
condition the output of U1b -- which swings negative when the Gate falls -- 
becomes clamped at one diode drop below 0V (to account for the drop across D4).

Stepping across D7 we go back up one diode drop, reaching 0V.  So the RC 
decay/release network is driven from 0V, and the resistance of D7 doesn't 
enter into the output result.  In a similar manner, D5 compensates D6.

When the output is near zero the resistances of the diodes becomes very 
large.  At this point, the feedback through R8 ensures that the final 
output matches the input.

Ian

At 06:08 AM 11/1/2014, Tom Wiltshire wrote:
>That's very neat, at least for a simple AD/AR case. And it works 
>beautifully. I've tried it in LTspice.
>
>Can you explain a bit more how it works please? I sort-of get it in 
>general (I think) but I'd like to properly understand it, if I'm to adapt 
>it for my ADSR situation.
>
>What I think is going on is something like this:
>Imagine a gate signal going into the non-inv input of U1B. U1B provides a 
>Gate-signal-with-gain at its output. The cap then charges towards this 
>boosted voltage level. Once the cap voltage gets within one diode drop of 
>the charging level, the diodes around U1B start to conduct, and the gain 
>on the Gate drops towards unity.
>
>I don't really get how the gain around U1B is limited to 
>the-gate-plus-one-diode-drop, although I can see that it's clearly because 
>of the back-to-back diodes in the feedback loop. I just don't see how. 
>This is where a lack of formal training in any of this stuff starts to be 
>a pain in the neck - again!. Still, I'm always learning.
>
>Thanks,
>Tom
>
>
>On 31 Oct 2014, at 18:36, Ian Fritz <ijfritz at comcast.net> wrote:
>
> > I just posted a typical scheme at Muff's:
> > http://www.muffwiggler.com/forum/viewtopic.php?p=1708948#1708948
> > No idea why other designs don't worry about this ... used to drive me 
> crazy.  This solution was published in EN many years ago ... can't 
> remember offhand who first came up with it.
> >
> > Clipping the envelope to zero when it gets to a small value also makes 
> sense.
> >
> > Ian
> >
> >
> >
> >
> > At 10:38 AM 10/31/2014, Tom Wiltshire wrote:
> >> Ian, Harald,
> >>
> >> Ok, thanks. That sounds exactly like what I'm looking at. The relevant 
> part of my circuit is very similar to this one, though I've done the 
> control logic very differently. The offset compensation is pretty much 
> the same too.
> >>
> >> http://www.cgs.synth.net/modules/cgs78_env.html
> >>
> >> Please correct me if I'm wrong, but what I understand is the following:
> >> As the cap decays towards zero, the voltage across it drops below the 
> 0.5V or so forward voltage of the diode, and the diode basically stops 
> conducting, or conducts only very slightly. This means that the final 
> part of the RC curve doesn't use R, but rather R+some big diode 
> resistance. This messes up the curve and makes the final portion take 
> aaaaagggggeeeeessss!
> >>
> >> So how can one prevent the diode from shutting off when we still need 
> it, without  making it conduct all the time? And if this is a very old 
> and well known problem, why do most of the current designs either not 
> bother with any compensation or only use a voltage offset compensation? 
> It must have been solved way back, no? But I can't find anything, aside 
> from a few linear envelopes which use op-amp integrators.
> >>
> >> Thanks,
> >> Tom
> >>
> >>
> >> On 31 Oct 2014, at 15:16, Harald <sdiy at haraldswerk.de> wrote:
> >>
> >> > A common problem if it uses diode switching. I tried to compensate 
> that for the Elektor Formant ADSR here: 
> http://www.haraldswerk.de/NGF/NGF_ADSR_F/NGF_ADSR_F_110.html. Sorry its 
> in German i still have to translate this site, but look at the schematic 
> for IC2C and IC2D.
> >> >
> >> > Am 31.10.2014 um 12:47 schrieb Tom Wiltshire:
> >> >> Hi All,
> >> >>
> >> >> I'm playing with an analog envelope generator at the moment. This 
> is something new for me since all the envelopes I've done thus far have 
> been digital.
> >> >>
> >> >> I noticed that there seems to be a 400mV offset on the output 
> voltage. However, when I started testing it, it seems like it is just the 
> very last bit of the release curve. The output rapidly falls from the 
> sustain level to about 300-400mV, but then takes another full 20 seconds 
> to reach something measurably close to zero.
> >> >>
> >> >> I realise that in theory it should *never* reach zero, but do all 
> analog envelopes behave like this? When you trigger a quick series of 
> envelopes, it amounts to a considerable offset (it would be several 
> semitones) in the interval between the envelopes. Are there tricks used 
> to eliminate this effect? I've checked several available ADSR schematics 
> and none of them seem to do anything different - a cap feeding a TL08x 
> voltage follower seems to be standard, and the cap just gets discharged 
> to ground. If what I'm seeing is typical, these designs should all have 
> this "offset."
> >> >>
> >> >> I'm just looking for some pointers really, since I don't know what 
> to expect.
> >> >>
> >> >> Thanks,
> >> >> Tom
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