[sdiy] G SSL clone RMS conversion

Tom Bugs admin at bugbrand.co.uk
Tue May 6 23:45:29 CEST 2014

Shady on terminologies.. but..

No log/multiplier - I think that's due to the internals of the DBX (or 
THAT replacement) chips perhaps?
I found on a forum post "DBX VCAs generally respond to a linear voltage 
with a logarithmic (dB) gain change"

I think you could call it RMS (but, again, terminology?!) - I tend to 
redraw such diagrams and, oh, then quickly realise the familiarity of 
the opamp diode arrangements.
Not entirely sure of the ratio arrangement, but if I read correctly:
1:2 ratio - just a resistor to -12V so a DC offset basically
1:4 ratio - small offset plus adjustment of the opamp stage gain (brings 
in resistor in parallel to main 1M feedback resistor)
1:10 ratio - similar but then you've also got the extra diode and +12V 
resistor - yep, not seen that before.

The Attack/Decay parts (cap, opamp buffer etc) seem kind of standard - I 
do imagine that these, combined with the rectifier stages before, should 
be shaping things - it is similar to many env. shapers.
I don't recall seeing another comp with sidechain VCA but then I haven't 
looked at that many..

Would be interesting to redo with 2164s!


On 06/05/2014 18:23, Justin Owen wrote:
> Hello - I hope nobody minds me posting this here and I hope a compressor design/build question isn't too far out of the SDIY remit...
> I've been looking into various RMS to DC conversion schems including the one from the DBX 160, TI app note SNOA855 and a similar schem in the Sergio Franco book that Byron Jacquot mentioned recently (which is great BTW - thanks!).
> Someone also pointed me to this schematic of a clone of the SSL Bus Compressor:
> http://www.gyraf.dk/gy_pd/ssl/ssl_sch.gif
> I assumed the RMS conversion started with the 2nd and 3rd op amp after the sidechain VCA (third 'row' down) but it appears to be just two full wave rectifier circuits - I can't see the log/multiplier part that appears in the other RMS conversion schems I've seen that is normally done with transistors or a diode array.
> I also can't quite work out how the R pairs are arranged around the SW1/Ratio (following the two HWRs).
> I've tried to sim the circuit and it appears to put out a narrow pulse from the negative rail to 0V at the same frequency of the signal at the sidechain input - not what I expected from an RMS output.
> Can anyone offer any insight as to what this part of the circuit is actually doing or how it might be working or something that is similar that I can compare it with?
> Thanks,
> - J
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