[sdiy] (Low) frequency to voltage conversion

Steve Lenham steve at bendentech.co.uk
Thu Mar 27 11:13:18 CET 2014

On 26/03/2014 22:09, Neil Johnson wrote:
> Steve Lenham wrote:
>> 0.001Hz? One cycle every 16.7 minutes?
>> Methinks any analogue solution is going to need some jolly large caps!
>> And the ripple on the output will be fearsome.
> The CESYG DuaLFO goes down to around 80-90 minutes, all-analogue, and 100n caps.
> And another example, the venerable HP 3310 goes down to around
> 0.0005Hz although that does use a 1uF capacitor on the lowest range.

Fair enough - that's impressive (though I'd imagine you need to be a 
pretty good analogue engineer to achieve that, whereas any novice 
programmer can get a micro to count clock cycles).

However, the OP was asking about frequency-to-voltage conversion, not 
the other way round - does that make any difference, or is it equally 
achievable in the analogue domain?


Steve L.

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