[sdiy] (Low) frequency to voltage conversion

Neil Johnson neil.johnson71 at gmail.com
Wed Mar 26 23:09:24 CET 2014

Steve Lenham wrote:
> 0.001Hz? One cycle every 16.7 minutes?
> Methinks any analogue solution is going to need some jolly large caps!
> And the ripple on the output will be fearsome.

The CESYG DuaLFO goes down to around 80-90 minutes, all-analogue, and 100n caps.

And another example, the venerable HP 3310 goes down to around
0.0005Hz although that does use a 1uF capacitor on the lowest range.


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